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Chapter 4

Chapter 4. Computer Architecture. Pep/9 virtual machine. Figure 4.1. The Pep/9 hardware consists of three major components at the instruction set architecture level, ISA3 :.

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Chapter 4

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  1. Chapter 4 Computer Architecture

  2. Pep/9 virtual machine

  3. Figure 4.1 • The Pep/9 hardware consists of three major components at the instruction set architecture level, ISA3: The bus is a group of wires that connects the three major components. It carries the data signals and control signals sent between the blocks.

  4. Figure 4.2 The CPU contains 6 registers.  X, PC, and SP—help the CPU access information in main memory.  negative, zero, overflow, and carry bits

  5. Figure 4.3 • 65,536 eight-bit(byte) storage locations • Each byte has an address (dec:0 to 65,535; hex:0000 to FFFF.) • Main memory is sometimes called core memory. byte2 byte3 byte1 Main memory of Pep/9 Computer

  6. Figure 4.4 Even though the lines have equal widths visually in the block, a single line may represent one or several bytes. The address on the side of the block is the address of the leftmost byte in the line. You can tell how many bytes the line contains by the sequence of addresses (3 bytes here). top bottom

  7. A Pep/9 word • word is a certain number of bytes • In the Pep/9 computer, a word is two adjacent bytes (16 bits). • Most of the registers in the Pep/9 CPU are word registers.

  8. Figure 4.5 • In main memory, the address of a word is the address of the first byte of the word.   Two adjacent bytes at addresses 000B and 000C. The address of the 16-bit word is 000B. To save space on the page, the content of a byte or word is usually written in hexadecimal

  9. Input/Output Devices • The Pep/9 system simulates two input/output (I/O) modes—interactive and batch. • Before executing a program, you must specify the I/O mode. • If you specify interactive: • the input comes from the keyboard • both input and output appear in a terminal window. • If you specify batch: • the input comes from an input pane and the output goes to an output pane. • simulates input from a file because the input pane must have data in it before the program executes

  10. Pep/9 use Memory-mapped I/O • input device is wired into main memory at one fixed address (FC15 in Pep/9) • output device is wired into main memory at another fixed address (FC16 in Pep/9). • DMA-Direct Memory Access • allows data to flow between the disk and main memory directly without going through the CPU • Pep/9 does not use this

  11. Data and Control • Data flow from the input device at address FC15 on the bus to the CPU. • Data can also flow from the CPU on the bus to the output device at address FC16 FC15 FC16

  12. Figure 4.6 Instruction Format • Each computer has its own set of instructions wired into its CPU • The Pep/9 computer has 40 instructions in its instruction set. • Each instruction consists of either a single byte called the instruction specifier, or the instruction specifier followed immediately by a word called the operand specifier. • Instructions that do not have an operand specifier are called unary instructions. 

  13. Figure 4.7

  14. Figure 4.6 Instruction Format • The Pep/9 computer has 40 instructions in its instruction set:

  15. Figure 4.6 (continued)

  16. Figure 4.6 (continued)

  17. The opcode • The eight-bit instruction specifier can have several parts: • Part1:operation code (opcode): •  may consist of as many as eight bits and as few as four. • E.g. • instruction to move the stack pointer to the accumulator • eight-bit opcode of 0000 0011. • E.g. • five-bit opcode 01010.

  18. Instructions with fewer than eight bits in the opcode • subdivide their instruction specifier into several fields depending on the instruction.  • indicates these fields with the letters a, r, and n. • Each one of these letters can be either 0 or 1. • E.g. • 2 versions of instruction: 0001-1000 and 0001-1001 • How many version in following?:

  19. Figure 4.8 letter a : addressing mode Pep/9 executes each nonunary instruction in one of eight addressing modes: Later chapters describe the meaning of the addressing modes. For now, it is important only that you know how to use the tables of Figures 4.7 and 4.8 to determine which register and addressing mode a given instruction uses

  20. Figure 4.8 (continued)

  21. Figure 4.8 (continued) letter r : register. instruction operates on the accumulator  instruction operates on the index register

  22. Question • Determine the opcode, register, and addressing mode of the 1100 1011 instruction

  23. Answer • Starting from the left, determine with the help of Figure 4.6 that the: • opcode is 1100 • r = 1   index register. • aaa = 011  stack relative addressing • Therefore, the instruction loads a word from memory into the index register using stack-relative addressing.

  24. Instructions: • are stored in main memory. • The address of an instruction in main memory is the address of the first byte of the instruction. • operand specifier: • For non-unary instructions, indicates the operand to be processed by the instruction.

  25. Figure 4.9 Example • two adjacent instructions stored in main memory at locations 01A3 and 01A6 The instruction at 01A3 is not-unary The instruction at 01A6 is unary

  26. the instruction at 01A3 has • Opcode: 0111 subtraction • 1101 = raaa • Register-r field: 1 • instruction operates on the index register • Addressing-aaa field: 101 • indexed addressing (to interpret operand specifier ) • Operand specifier: 0000 0011 0100 1110

  27. The unary instruction at 01A6 has • Opcode: 0000 110 • arithmetic shift right • Register-r field: 0 • operation done on accumulator

  28. Machine language • binary sequence that CPU interprets according to the opcodes of its instruction set. • 0111 1101 0000 0011 0100 1110 • 0000 1100 • two instructions in hexadecimal, preceded by their memory addresses: • 01A3 7D034E • 01A6 0C

  29. The stop instruction • Instruction specifier: 0000 0000 • Causes the computer to stop

  30. Direct addressing • An addressing-aaa field of 001 indicates direct addressing. • The operand specifier is the memory address of the operand. • In mathematical notation, • Oprnd = Mem[OprndSpec]

  31. The load word instruction • Instruction specifier: 1100 raaa • Loads one word (two bytes) from memory to register r

  32. Figure 4.10, 4.11 • Example load word instruction: C1004A Address of operand in memory = 004A (where data read from) Load Word From memory Accumulator A Direct Addressing SEND_DATA DATA 1 in sign bit = negative The V and C bits are unaffected by the load word instruction. bit pattern is not all 0’s 92EF = 1001-0010 1110-1111

  33. The store word instruction • Instruction specifier: 1110 raaa • Stores one word (two bytes) from register r to memory

  34. Figure 4.12, 4.13 Address of memory where data needs To be stored = 004A Store Word To memory Index Register X Direct Addressing • Example store word instruction: E9004A

  35. The add instruction • Instruction specifier: 0110 raaa • Adds one word (two bytes) from memory to register r

  36. Figure 4.14, 4.15 Address of operand in memory = 004A (where data read from) Instruction Register X Add Word From memory • Example add word instruction: 69004A Direct Addressing 5 + (–7) = –2(dec), = FFFE (hex) –7 (dec) = FFF9 (hex)

  37. The subtract instruction • Instruction specifier: 0111 raaa • Subtracts one word (two bytes) in memory from register r

  38. Figure 4.16, 4.17 Address of operand in memory = 004A (where data read from) Accumulator A Subtract Word In memory from r • Example subtract instruction: 71004A Direct Addressing  3 – 9 = –6(dec) = FFFA (hex)

  39. The and instruction • Instruction specifier: 1000 raaa • ANDs one word (two bytes) from memory to register r

  40. Figure 4.18, 4.19 Address of operand in memory = 004A (where data read from) Instruction Register X Bitwise AND To r • Example AND word instruction: 89004A Direct Addressing 5DC3 AND 00FF = 00C3

  41. The or instruction • Instruction specifier: 1001 raaa • ORs one word (two bytes) from memory to register r

  42. Figure 4.20 Address of operand in memory = 004A (where data read from) Instruction Register X Bitwise OR To r • Example OR word instruction: 99004A Direct Addressing 1 9 5DC3 OR 00FF = 5DFF

  43. The invert instruction • Instruction specifier: 0000 011r • Bit-wise NOT operation on register r • Each 0 changed to 1, each 1 changed to 0

  44. Figure 4.21, 4.22 Accumulator A Invert bits in r NOT 0003 = FFFC

  45. The negate instruction • Instruction specifier: 0000 100r • Negate (take two’s complement of) register r

  46. Figure 4.23 Accumulator A negate r 1 0 0 8 - 3(dec) = 1111 1111 1111 1101 (bin) = FFFD (hex)

  47. The load byte instruction • Instruction specifier: 1101 raaa • Loads one byte from memory to the right half of register r Byte instruction: operate on a single byte of information

  48. Figure 4.24, 4.25 Accumulator A Load byte to r Memory address 4A Direct Addressing 92 loaded to right byte of A

  49. The store byte instruction • Instruction specifier: 1111 raaa • Stores one byte from the right half of register r to memory

  50. Figure 4.26 Accumulator A Store byte from r to mem Memory address 4A Direct Addressing 1 1 1 1 F

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