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EE2174: Digital Logic and Lab

Explore binary addition, half/full adders, n-bit adders, and carry mechanisms in digital logic design. Learn circuit implementation and design methodologies for arithmetic modules.

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EE2174: Digital Logic and Lab

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  1. EE2174: Digital Logic and Lab Professor ShiyanHu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 8 Arithmetic

  2. Overview • Binary Addition • Complement forms • Subtraction • Multiplication Arithmetic

  3. Objectives of This Lecture Arithmetic • What have we learned? • Combinational Circuit Basics • Three Design Methodologies • What are we going to learn? • Applying the above knowledge to design Adder • This is the most fundamental arithmetic module design

  4. 1-bit Addison • Performs the addition of two binary bits. • Four possible operations: • 0+0=0 • 0+1=1 • 1+0=1 • 1+1=10 • Circuit implementation requires 2 outputs, one to indicate the sum and the other to indicate carry. Arithmetic

  5. Half Adder: Definition • A half adder is to perform a 1-bit addition. • Inputs: A0, B0 • Outputs: S0, C1 • Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. • Boolean equations: • S0 = A0 B0 • C1 = A0B0 Truth Table Arithmetic

  6. Half Adder: Implementation • S0 = A0 B0 • C1 = A0B0 • The output of a half adder are AND and XOR results of the two given input bits. Block Diagram Logic Diagram B0 A0 A0 1 bit half adder S0 C1 B0 S0 C1 Arithmetic

  7. n-bit Addition • Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out. • Example: Let n=4Cout C3 C2 C1 C01 1 0 1 0 A3 A2 A1 A0 1 1 0 1 +B3 B2 B1 B0 +1 1 0 1 -------------- ---------- S3 S2 S1 S0 1 0 1 0 Arithmetic

  8. Full Adder: Definition • In a half adder, only two input bits are considered. • What if there is a carry from the less significant bits? • A full adder is to perform the additions of 3 bits, i.e., two input bits and a carry-in bit. Arithmetic

  9. Full Adder: Implementation (1) • The K-maps for • Ci+1: • Si: BiCi Ai 0 0 1 0 0 1 1 1 BiCi Ai 0 1 0 1 1 0 1 0 Arithmetic

  10. Full Adder: Implementation (2) • Boolean equations: • Ci+1 = AiBi + AiCi + BiCi • Si = AiBi’ Ci’ + Ai’Bi’Ci + Ai’BiCi’ + AiBiCi = Ai Bi Ci • You can design a full adder directly from the above equations (requires 3 ANDs and 1 OR for Ci+1 and 2 XORs for Si) • Can we do better? Arithmetic

  11. Observations • Derivation • Ci+1 = AiBi + AiBi’Ci+ Ai’BiCi = AiBi + (AiBi’ + Ai’Bi)Ci = AiBi + (Ai Bi)Ci • and Si = Ai Bi Ci • Why it helps? • We can first compute AND and XOR results among Ai and Bi, i.e., AiBiand Ai Bi, using a half adder. • Let Di=Ai Bi. • Next we can compute DiCi and Di  Ci using the other half adder. Arithmetic

  12. Full Adder by 2 Half Adders Ai Bi Ai 1 bit full adder Ci+1 Ci Si Bi Si Ci+1 Ci Arithmetic Arithmetic PJF - 12 23-Oct-19 A full adder can be implemented using two half adders and an OR gate.

  13. Exercise 1 Arithmetic • How many gates are reduced by the half adder based implementation? • How many transistors are needed in the half adder based implementation? • See page 35 in chapter 4 • 34 transistors

  14. n-bit Combinational Adders • Perform multi-bit addition • How? Arithmetic

  15. n-bit Ripple Carry Adder • It is constructed using n 1-bit full adder blocks. • Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position. Arithmetic

  16. Example: 4-bit Ripple Carry Adder C4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 -------------- S3 S2 S1 S0 Arithmetic

  17. Characteristics of Ripple Carry Adder Arithmetic Simple design What is the limitation?

  18. Ripple Carry Adder Delay • Circuit delay in an n-bit ripple carry adder is determined by the delay on the carry path from the LSB (C0) to the MSB (Cn). • Let the delay in a 1-bit FA be D. The delay of an n-bit ripple carry adder is nD since it is a sequential computation. Arithmetic

  19. Exercise 2 A127 ,…………………………….…., A0 B127 ,……………………………..…., B0 128 bits Arithmetic What could be a potential improvement in terms of delay? Suppose that two 128-bit numbers are to be added.

  20. Main Idea: Predict Carry In A127 ,………., A64 A63 ,………., A0 B127 ,………., B64 B63 ,………., B0 64 bits 64 bits C64=0 A127 ,………., A64 B127 ,………., B64 64 bits C64=1 Arithmetic Use three 64-bit adders One computes the lower 64 bits, one computes higher 64 bits assuming the carry in C64 is 0, and one computes higher 64 bits assuming the carry in C64 is 1. All three adders compute simultaneously After that, one knows the right carry in C64. One just needs to pick the correct result corresponding to the right C64.

  21. Advantage and Limitation Arithmetic • What is the delay? • 64 D for each adder • Assuming that picking time is also D, total delay is 65 D. • What is the limitation? • To add two n-bit numbers, what is the best delay? • Implementation?

  22. Summary of This Lecture Arithmetic A half adder adds 2 input bits but not the carry in bit. A full adder adds 2 input bits and the carry in bit. A fully adder can be efficiently implemented using 2 half adders and an OR gate. A ripple carry adder consists of n full adder sequentially to perform n bit addition. It is simple but with significant delay which needs improvement.

  23. Decimal Arithmetic • Design circuits that perform decimal arithmetic such as addition and multiplication. • Input is in binary coded form in BCD • BCD Decimal Adder • 4 bits per decimal number as input • 5 bits as output indicate the decimal sum and the carry • Remember BCD addition rules. • Add 0110 to the sum if it is greater than or equal to 1010 • That is, 1010, 1011, 1100, 1101, 1110, 1111 Arithmetic

  24. Addend Addend C = K + z3z2 + z3z1 K 4-bit binary adder z3 z2 z1 z0 C 0 4-bit binary adder S3 S2 S1 S0 BCD sum Binary Coded Decimal (BCD) Adder Arithmetic

  25. 2’s Complement • For a positive n digit number N2 in binary, the 2's complement, 2C(N2), is given by: • 2C(N2) = 2n-N2 , if n > 0 0 , if n = 0 • Example: N2 =1010 • 2C(N2) = 24-N2 = 100002 – 10102 = 01102 • Example: N2 =11111 • 2C(N2) = 25-N2 = 1000002 – 111112 = 00001 2 { Arithmetic

  26. 2’s Complement (cont.) • Here’s an easier way to compute the 2’s complement: • Leave all least significant 0’s and first 1 unchanged. • Replace 0 with 1 and 1 with 0 in all remaining higher significant bits. • Examples: • N = 1010 N = 01011000 01 10 10101000 Arithmetic

  27. 1’s Complement • For a positive n digit number N2 in binary, the 1's complement, 1C(N2), is given by: • 1C(N2) = (2n-1) - N2 • Example: N2 =011 • 1C(N2) = (23-1)-N2 = 1112 – 0112 = 1002 • Example: N2 =1010 • 1C(N2) = (24-1) - N2 = 11112 – 10102 = 0101 2 • Observation: 1’s complement can be derived by just complementing all the bits in the number. Arithmetic

  28. Observation • Compare 1’s complement with 2’s complement: • 2n-N= [(2n-1) - N] + 1 • Thus, the 2’s complement can be obtained by deriving the 1’s complement and adding 1 to it. • Example: • N = 1001 • 2C(N) = 24 – N = 10000 – 1001 = 0111 • 1C(N) = 24 – 1 - N = 1111 – 1001 = 0110  2C(N) = 1C(N) + 1 = 0110 + 0001 = 0111 Arithmetic

  29. Subtraction with 2’s complement • A-B can be simply computed as A+2C(B) and deleting the leading the carry 1 • 7-3 • (111)-(011)=(111)+(101)=(1100) • delete the carry which gives (100) Arithmetic

  30. Subtraction with 1’s complement • A-B can be simply computed as A+1C(B), deleting the carry and adding 1 • 7-3 • (111)-(011)=(111)+(100)=(1011) • Delete carry which gives (011) • Add 1 which gives (100) Arithmetic

  31. Binary Adder/Subtractors • If we perform subtraction using complements, we eliminate subtraction operation, and thus, can use an adder with appropriate complementer for subtraction. • Thus, to form an adder-subtractor circuit, we only need a selective complementer and an adder. • The subtraction A-B can be performed by taking the 2's complement of B and adding to A. • The 2's complement of B can be obtained by complementing B and adding one to the result. A-B = A + 2C(B) = A + 1C(B) + 1 = A + B’ + 1 Arithmetic

  32. 4-bit Binary Adder/Subtractor • XOR gates act as programmable inverters Arithmetic

  33. 4-bit Binary Adder/Subtractor (cont.) • When S=0, the circuit performs A + B. The carry in is 0, and the XOR gates simply pass B untouched. • Assume that A > B. When S=1, the carry into the least significant bit (LSB) is 1, and B is complemented (1’s complement) prior to the addition; hence, the circuit adds to A the 1’s complement of B plus 1 (from the carry into the LSB). Arithmetic

  34. 4-bit Binary Adder/Subtractor (cont.) S=0 B3 B2 B1 B0 0 S=0 selects addition Arithmetic

  35. 4-bit Binary Adder/Subtractor (cont.) S=1 B3’ B2’ B1’ B0’ 1 S=1 selects subtraction Arithmetic

  36. Binary Multiplier • Binary multiplication resembles decimal multiplication: • n-bit multiplicand is multiplied by each bit of the m-bit multiplier, starting from LSB, to form n partial products. • Each successive set of partial products is shifted 1 bit to the left. • Derive result by addition the m rows of partial products. Arithmetic

  37. Binary Multiplier Circuit2-bit by 2-bit multiplier Half Adders are Sufficient since there is no Carry-in in addition to the two inputs to sum Arithmetic

  38. Summary • Binary Addition • Complement forms • Subtraction • Multiplication Arithmetic

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