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Computer Architecture

Computer Architecture. Lecture 10 EXCEPTIONS AND INTERRUPTS. Exceptions and Interrupts.

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Computer Architecture

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  1. Computer Architecture Lecture 10 EXCEPTIONS AND INTERRUPTS

  2. Exceptions and Interrupts • Exception handling is a programming language construct or computer hardware mechanism designed to handle the occurrence of some condition that changes the normal flow of execution. The condition is called an exception. Alternative concepts are interrupt, signal and event handling. • In general, current state will be saved in a predefined location and execution will switch to a predefined handler (subroutine/procedure). Depending on the situation, the handler may later resume the execution at the original location, using the saved information to restore the original state. For example, an exception which will usually be resumed is a page fault, while a division by zero usually cannot be resolved transparently. (Wikipedia)

  3. Common Exceptions • I/O Device Request • Integer Arithmetic Overflow • FP Arithmetic Anomaly • Page Faults • Memory Protection Violation • Undefined Instruction • Power Failure • etc

  4. Characterizing Exceptions • Synchronous vs. Asynchronous • User Requested (system calls)/Coerced (mouse click) • Maskable vs. Non-maskable • Within / Between Instructions • Resume-able/Terminate

  5. Resumable • Shut pipeline by converting all instruction after the instruction causing exception to NOP • Save processor state • Call Handler • Resume State • Precise Exception ???

  6. MIPS Interrupts • IF – Page Fault, MPV • ID – Undefined or Illegal Op Code • EX – Arithmetic • MEM – Same as IF • WB – None

  7. MULTIPLE CYCLE PIPELINES

  8. Single Clock Cycle Single Cycle Computer (One Big Clock Cycle to Accommodate Longest Latency) IF ID EXE WB

  9. EX IF ID WB IF IF ID ID EX EX WB WB Multiple Cycle Computers All Instruction Go through the Processing One-by-One

  10. IF ID EX Mem WB Classic 5-Stage Integer Pipeline Almost 1 CPI except for LUD and Branch Hazards

  11. A Multiple Cycle Pipeline Register File (Integer/FP) EX FP ADD IF ID Mem WB FP Multiply Register File (Integer/FP) Divide Register File

  12. EX IF ID A 1 A 2 A 3 A 4 Mem WB M 1 M 2 .. M 7 Divide Multiple Cycle Floating Point Pipeline

  13. EX IF ID A 1 A 2 A 3 A 4 Mem WB M 1 M 2 .. M 7 Divide Forwarding ALU/FP Instructions

  14. Example 1 Without Forwarding With Forwarding

  15. EXAMPLE 2

  16. EXAMPLE 3 DIV Unit is not Pipelined. So second instruction waits in ID stage although it is independent.

  17. Example 4 - Out Of Order Execution Note All Instructions Independent Out Of Order Completion

  18. Example 5 Structural Hazard

  19. Example 6 - WAW Reg Busy bit in Register File A particular processor – it waits in ID stage in case of WAW not in WB, Page A-54, Paragraph 2

  20. Example 7 • L.D F4, 0(R2) • MUL.D F0,F4,F6 • ADD.D F2,F0,F8 • S.D F2,0(R2)

  21. Example 8 - EXCEPTIONS • DIV.D F0,F1,F2 • ADD.D F10,F10,F8 • SUB.D F12,F12,F14

  22. Data Hazards • RAW Hazard ADD.D F3, F1, F2 SUB.D F5, F6, F3 • WAW Hazard DIV.D F3, F1, F2 SUB.D F3, F6, F5 • WAR Hazard DIV.D F3, F1, F2 SUB.D F5, F6, F3 ADD.D F3, F6, F7

  23. TOO MANY ID STAGE STALLS – SOLUTION?

  24. THE SCOREBOARD Next Time

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