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A 30-GS/sec Track and Hold Amplifier in 0.13- µm CMOS Technology

A 30-GS/sec Track and Hold Amplifier in 0.13- µm CMOS Technology. Shahriar Shahramian Sorin P. Voinigescu Anthony Chan Carusone Department of Electrical & Computer Eng. University of Toronto Canada. Digital Equalizer. Photo Detector. ADC. Adaptive Equalizer. Equalized Data. T/H.

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A 30-GS/sec Track and Hold Amplifier in 0.13- µm CMOS Technology

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  1. A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology Shahriar Shahramian Sorin P. Voinigescu Anthony Chan Carusone Department of Electrical & Computer Eng. University of Toronto Canada

  2. Digital Equalizer Photo Detector ADC Adaptive Equalizer Equalized Data T/H Clock Recovery Introduction & Motivation I • Equalization required at high bit rates • Analog equalization up to 40 Gb/s • Digital equalization is more robust and flexible • Require full rate Track & Hold Amplifiers

  3. Introduction & Motivation II • Demonstrated 40-GS/sec THA in SiGe BiCMOS • fT and fMAX of 160 GHz • CMOS technologies scaling to nanometre • fT and fMAX exceed 200 GHz for in production CMOS • CMOS is a serious contender for implementing DSP based equalizers above 10 Gb/s

  4. J. C. Jensen, et. al. S. Shahramian, et. al. CICC 02 CSICS 05 Introduction & Motivation III Diode Sampling Bridge Switched Emitter Follower • High speed • Low dynamic range • Requires diodes • High speed • Lower supply • Isolation in hold mode

  5. I. H. Wang, et. al. This work Electronic Letters 06 CICC 06 Introduction & Motivation IV Series CMOS Sampler Switched Source Follower • Low supply • Low speed due to series CMOS RON • Take advantage of high speed CMOS source follower

  6. 0.13-µm CMOS Technology • Simulated fT and fMAX of 80 GHz • 8 layer metallization back end with thick RF top metal layers • Available triple-well CMOS transistors • Available low power (high VTH) transistors

  7. CML INV CS TIA CML INV CML INV Clock CS Clock Path THA Block Diagram Data Path DRV CS TIA T/H Diff. Pair Diff. Pair Input Output DRV CS

  8. TIA Input Stage Design Active loads Improve open loop Gain, T

  9. TIA Input Stage Design Eliminating current source transistor reduces power supply voltage

  10. TIA Input Stage Design Signal matching through resistive feedback

  11. TIA Input Stage Design Noise matching through transistor sizing

  12. TIA Input Stage Design Transistors biased at J= 0.25 mA/µm, increased noise figure for higher bandwidth Simulated bandwidth: 30 GHz Simulated input integrated noise over 30 GHz: 0.5 mVrms

  13. TIA Input Stage Design Inductors improve bandwidth, input matching and filter high frequency noise

  14. CS TIA CS Input Stage Design Transistors Q1 and Q2 are diode-connected at DC and therefore can bias the next CS stage

  15. T/H THA Stage Design Switched source follower for maximum bandwidth

  16. T/H THA Stage Design During Track, QSF acts as a source follower with current IT

  17. T/H THA Stage Design During Hold, IT flows through RL which turns QSF off and isolates CH

  18. T/H THA Stage Design QT and QH operate in digital mode and thus are biased at J = 0.15mA/µm

  19. T/H THA Stage Design High VTH devices are used to drive QT further into “OFF” region and reduce leakage

  20. T/H THA Stage Design QSF is implemented as a triple well transistor to reduce VEFF and lower power supply voltage

  21. Diff. Pair T/H THA Stage Design A linear buffer drives the T/H block with 600mVPP input and output swing

  22. Diff. Pair T/H THA Stage Design Capacitor Cfth is used to match QSF-CGS and thus cancel input signal feedthrough during hold mode

  23. DRV Diff. Pair DRV T/H THA Stage Design A linear output driver provides signal to external 50Ω resistors and measurement equipment

  24. CML INV CML INV CML INV Clock Distribution Converts a single-ended 30-GHz clock signal to a differential signal with 750mVPP swing

  25. Chip Micrograph • Manufactured using IBM’s 0.13µm CMOS technology • The circuit operates from a 1.8V supply and consumes 150mA. TIA CS Diff. Pair Diff. Pair DRV THA CML INV CML INV 1mm CML INV TIA CS 1mm

  26. Measurement Results: SP

  27. Measurement Results: SP II

  28. Time Domain

  29. Frequency Domain I

  30. Frequency Domain II

  31. Frequency Domain III

  32. Circuit Comparison

  33. Conclusion • CMOS emerges as a contender for high speed DSP based equalizers • Discussed the design methodology for CMOS switched source follower THA • Demonstrated the first 30-GS/sec THA in CMOS

  34. Acknowledgement • CMC for chip fabrication and providing CAD tools • NSERC for financial support • OIT and CFI for equipment • ECIT for providing the network analyzer

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