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System on Chip (SoC) Architecture Design SOCks – FPU Example

System on Chip (SoC) Architecture Design SOCks – FPU Example. James E. Stine. All calculations are done in double precision. Single-to-Double conversion. Mantissa. Sign. Dadda Multiplier. Exponent. Sticky Bit Postnormalization Rounding. Output. Structure of Floating Point Multiplier.

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System on Chip (SoC) Architecture Design SOCks – FPU Example

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  1. System on Chip (SoC) Architecture DesignSOCks – FPU Example James E. Stine

  2. All calculations are done in double precision Single-to-Double conversion Mantissa Sign Dadda Multiplier Exponent Sticky Bit Postnormalization Rounding Output Structure of Floating Point Multiplier

  3. Dadda Multiplier Partial Products Compression (Half Adder) Compression (Full Adder) Final Carry-Propagate Adder

  4. Arbiter AMBA Interface Address and Control Mux HADDR HADDR SLAVE 1, Floating Point Unit HWDATA HWDATA MASTER 1, LEON HRDATA HRDATA Address = 0xA016_0000 HADDR HWDATA MASTER n HADDR HWDATA SLAVE n HRDATA HRDATA The Floating Point Unit is interfaced with the LEON through the AHB AMBA interface (Advanced High-Performance Bus). This bus is intended to provide a high-speed communication with the processor. Read Data Mux Decoder

  5. AMBA Interface A typical AMBA AHB system includes: • AHB Master: Initiates read or write operations on the bus. Only one Master is allowed to access the bus at a time. • AHB Slave: AHB Slave responds to a read or write, given an address-space range. It then responds with acknowledge, wait or fail signal to the requesting master. • AHB Arbiter: The arbiter is responsible for allowing access to the bus to only one Master at any time. The arbitration algorithm may be modified. • AHB Decoder: A single decoder is required for all AHB devices. It is used to decode the address of each transfer and provide a select signal for the involved slave in that transfer.

  6. Data input from CPU [26:0] match_FPSCR address & Write Enable (write to FPSCR?) 27 1 FPSCR Register FLAGS SP/DP Result OpB OpA FSM Control [31:27] [26:16] [15] [14:10] [9:5] [4:0] FPSCR_OUT, [19:16] Traps, SP/DP, Rounding, etc 1 F P S C R O u t fpu_CPU 5 Single/Double Precision Bit [15] 1 5 Address input from CPU 32 0 1 Address Input (0-31) Operand A Address Operand B Address 1 Write Enable Data input from CPU 32 0 1 AMBA Module address match & CPU Write Enable Register File 32 x 32-bit Data Input (CPU Write) Data Input extended 32-bits (double precision) Data Output (CPU Read) 32 0 1 Data output to CPU 32 Operand A Data Operand B Data fpu_CPU 5 FPSCR Out 1 64 64 From FSM Control FPSCR Address match (fpscr_match) Floating Point Unit 4 From FPSCR output [19:16] Traps, Round Mode, SP/DP FLAGS (Invalid, UDF, OVF, Inexact, DivZero) 32 Result [63:32] [31:0] 32 AMBA AHB / FPU Interface

  7. SOCks FP MultiplierStep-by-step • Check if sufficient disk space is available“quota –v” • Get SOCks kit and install it(package created by Johannes Grad from Illinois Institute of Technology)“tar xvf /import/vlsi7/jgrad/socks/socks.tar” • Make sure that RTEMS is installed(Real-Time Operating System for Multiprocessor Systems) • Set the path to RTEMS “set path = (/opt/rtems/bin $path)” • Test if the path was added“which sparc-rtems-g++”

  8. SOCks FP MultiplierStep-by-step • Go to ./firmware directory“cd ./firmware” • Create a new source code folder by copying other example to a new directory.“cp –r bubblesort project_name” • Modify main test file (leon_test.c) and other necessary files (misc.c, test.h, leon.h). Additional modifications were necessary because additional structure vint was introduced. • Compile the firmware“make” • After successful compilation go to HDL custom directory.“cd ../../hdl/custom”

  9. SOCks FP MultiplierStep-by-step • Digital Logic stored in HDL/custom directory communicates with Leon processor through AMBA bus. • Put FPU files in custom directory. • Compiler is set to compile all Verilog files that are stored in hdl/custom directory. In this case VHDL was used so change was necessary. Following line was added to exe/socks_compile“ncvhdl –v93 –work customlib ./custom/*.vhd” • Go to HDL directory“cd ..” • Compile the custom logic HDLIn this context compilation means building a HDL simulation model, not a binary code as in C++ compilation.“../exe/socks_compile”

  10. SOCks FP MultiplierStep-by-step • After successful HDL compilation go to sim directory“cd ../sim” • Run the simulation • “../exe/socks_sim project_name” • “../exe/socks_sim project_name partial”(creates waveforms for the custom logic) • “../exe/socks_sim project_name full”(creates waveforms for the entire design) • View the waveforms if needed“simvision &” • Remove temporary files to save space“cd ..”“exe/socks_clean”

  11. SOCks FP MultiplierStep-by-step

  12. SOCks FP MultiplierStep-by-step

  13. SOCks FP MultiplierStep-by-step

  14. SOCks FP MultiplierStep-by-step

  15. SOCks FP MultiplierStep-by-step

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