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Introduction to VHDL Part 2

Introduction to VHDL Part 2. Fall 08. We will use Std_logic. And, Or have same precedence See slide 8 of part 1. library IEEE; use IEEE.std_logic_1164.all; ENTITY and2 is GENERIC(trise : time := 10 ns; tfall : time := 5 ns); PORT(a : IN std_logic; b : IN std_logic;

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Introduction to VHDL Part 2

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  1. Introduction to VHDLPart 2 Fall 08

  2. We will use Std_logic And, Or have same precedence See slide 8 of part 1.

  3. library IEEE; use IEEE.std_logic_1164.all; ENTITY and2 is GENERIC(trise : time := 10 ns; tfall : time := 5 ns); PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END and2;

  4. ARCHITECTURE behav OF and2 IS BEGIN one : PROCESS (a,b) BEGIN IF (a = '1' AND b = '1') THEN c <= '1' AFTER trise; ELSIF (a = '0' OR b = '0') THEN c <= '0' AFTER tfall; ELSE c <= 'X' AFTER (trise+tfall)/2; END IF; END PROCESS one; END behav;

  5. library IEEE; use IEEE.std_logic_1164.all; ENTITY tb IS END tb; ARCHITECTURE test OF tb IS SIGNAL a, b, y, z: std_logic; BEGIN and_y: entity work.and2(behav) GENERIC MAP(tfall => 15 ns) PORT MAP(a, b, y); and_z: entity work.and2(behav) PORT MAP(a, b, z); PROCESS CONSTANT period: time := 40 ns; BEGIN a <= '1'; b <= '0'; WAIT FOR period; a <= '1'; b <= '1'; WAIT FOR period; a <= '0'; b <= '1'; WAIT FOR period; a <= '0'; b <= '0'; WAIT; END PROCESS; END TEST; -- Same as -- a <= '1', '0' after 2*period; -- b <= '0', '1' after period, '0' after 3*period;

  6. Typical programming language Compilation Link and Load Execute VHDL Analysis Check design unit for errors Elaboration Check design hierarchy Simulation Synthesis Development steps

  7. Analysis • Check for syntax and semantic errors • syntax: grammar of the language • semantics: the meaning of the model • Analyze each design unit separately • entity declaration • architecture body • … • Usually each design unit consisting of an entity and its architecture is in a separate file, but multiple design units can be combined in the same file. • Analyzed design units are placed in a library • in an implementation dependent internal form • current library is called work

  8. Elaboration • “Flattening” the design hierarchy • create ports • create signals and processes within architecture body • for each component instance, copy instantiated entity and architecture body • repeat recursively • bottom out at purely behavioral architecture bodies • Final result of elaboration • flat collection of signal nets and processes

  9. Modeling Interfaces • Entity declaration (see Fig 1-7 p 9) • describes the input/output ports of a module entity name port names port mode (direction) entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit );end entity reg4; punctuation reserved words port type

  10. VHDL-87 • Omit entity at end of entity declaration entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit );end reg4;

  11. Architecture Styles • Behavioral – High level architecture defiend in terms of its operation over time. • Data flow or RTL – Register transfers. • Structural – A collection of components.

  12. Modeling Behavior • Architecture body • describes an implementation of an entity • may be several per entity • Behavioral architecture • describes the algorithm performed by the module • contains • process statements, each containing • sequential statements, including • signal assignment statements and • wait statements

  13. Behavior Example architecture behav of reg4 isbegin storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;beginif en = '1' and clk = '1' then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;end if; q0 <= stored_d0 after 5 ns; q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;wait on d0, d1, d2, d3, en, clk;end process storage; end architecture behav;

  14. VHDL-87 • Omit architecture at end of architecture body • Omit is in process statement header architecture behav of reg4 isbegin storage : process ...begin ...end process storage; end behav;

  15. Modeling Structure • Structural architecture • implements the module as a composition of subsystems • contains • signal declarations, for internal interconnections • the entity ports are also treated as signals • component instances • instances of previously declared entity/architecture pairs • port maps in component instances • connect signals to component ports • wait statements

  16. Structure Example

  17. Structure Example • First declare D-latch and and-gate entities and architectures entity d_latch isport ( d, clk : in bit; q : out bit );end entity d_latch; architecture basic of d_latch isbegin latch_behavior : process isbeginif clk = ‘1’ then q <= d after 2 ns;end if;wait on clk, d;end process latch_behavior; end architecture basic; entity and2 isport ( a, b : in bit; y : out bit );end entity and2; architecture basic of and2 isbegin and2_behavior : process isbegin y <= a and b after 2 ns;wait on a, b;end process and2_behavior; end architecture basic;

  18. Structure Example architecture struct of reg4 is signal int_clk : bit; begin bit0 : entity work.d_latch(basic)port map ( d0, int_clk, q0 ); bit1 : entity work.d_latch(basic)port map ( d1, int_clk, q1 ); bit2 : entity work.d_latch(basic)port map ( d2, int_clk, q2 ); bit3 : entity work.d_latch(basic)port map ( d3, int_clk, q3 ); gate : entity work.and2(basic)port map ( en, clk, int_clk ); end architecture struct; • Now use them to implement a register

  19. VHDL-87 • Can’t directly instantiate entity/architecture pair • Instead • include component declarations in structural architecture body • templates for entity declarations • instantiate components • write a configuration declaration • binds entity/architecture pair to each instantiated component

  20. Structure Example in VHDL-87 • First declare D-latch and and-gate entities and architectures entity d_latch isport ( d, clk : in bit; q : out bit );end d_latch; architecture basic of d_latch isbegin latch_behavior : processbeginif clk = ‘1’ then q <= d after 2 ns;end if;wait on clk, d;end process latch_behavior; end basic; entity and2 isport ( a, b : in bit; y : out bit );end and2; architecture basic of and2 isbegin and2_behavior : processbegin y <= a and b after 2 ns;wait on a, b;end process and2_behavior; end basic;

  21. Structure Example in VHDL-87 • Declare corresponding components in register architecture body architecture struct of reg4 is component d_latchport ( d, clk : in bit; q : out bit );end component; component and2port ( a, b : in bit; y : out bit );end component; signal int_clk : bit; ...

  22. Structure Example in VHDL-87 • Now use them to implement the register ... begin bit0 : d_latchport map ( d0, int_clk, q0 ); bit1 : d_latchport map ( d1, int_clk, q1 ); bit2 : d_latchport map ( d2, int_clk, q2 ); bit3 : d_latchport map ( d3, int_clk, q3 ); gate : and2port map ( en, clk, int_clk ); end struct;

  23. Structure Example in VHDL-87 • Configure the register model configuration basic_level of reg4 is for struct forall : d_latchuse entity work.d_latch(basic);end for; forall : and2use entity work.and2(basic)end for; end for; end basic_level;

  24. VHDL Reserved Words

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