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Lecture 4: Data Types and Operators

Lecture 4: Data Types and Operators. Data Types Review. Verilog support two families of pre-defined variables Nets Connectivity Variables: Nets Data Storage Variables: Registers wire output_bits; //declare a net A net must be driven by a primitive gate or by a continuous assignment

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Lecture 4: Data Types and Operators

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  1. Lecture 4: Data Types and Operators

  2. Data Types Review • Verilog support two families of pre-defined variables • Nets • Connectivity Variables: Nets • Data Storage Variables: Registers • wire output_bits; //declare a net • A net must be driven by a primitive gate or by a continuous assignment • All connectivity variables in the following are nets. • wire, tri, wand, wor, triand, trior, • supply0, supply1, tri0 (pull to 0), tri1 (pull to 1) • trireg (models charge storage on a net) • Only trireg stores value, all others must be driven. • undeclared identifiers are implicit wires

  3. Data Type Review • Registers • Data Storage Variables: reg • reg //store a logic value • integer //support procedural computation • time //provide access to simulation time • real //store delay parameters as real numbers • reg [15:0] m[0:8191]; //8192 x 16 bit memory

  4. Variable Type and Port Mode • rules for data types at ports • port mode • variable type input output inout • net yes yes yes • reg no yes no

  5. Verilog: Operators • Verilog has the following operators for continuous assignments • and register manipulations • { , } concatenation • Arithmetic Operators: +, -, *, / , % (modulus) • Bitwise Operators: produce a binary word result by • operating bitwise on a pair of operands. • ~ bitwise nagation • $ bitwise and • | bitwise or • ^ bitwise exclusive or (XOR) • ~^ bitwise exclusive nor (XNOR)

  6. Reduction Operators • Reduction Operators: producing a single bit value by • operating on a single data word. • & reduction and • | reduction or • ~& reduction nand • ~| reduction nor • ^ reduction exclusive or • ~^ reduction xnor

  7. Logical Operators • Logical operators are used to operate on Boolean operands to produce a Boolean result. • The operands may be a net, register, or expression that is evaluated to produce a result. • ! logical negation • && logical and • || logical or • == logical equality • != logical inequality • === case equality • !== case inequality • if (( a < size -1) && ( b != c) && (index != last_one)) .... • if ( !inword) ... • if ( inword == 0) ...

  8. Relational Operators • Relational operators compare operands and produce a Boolean (true or false ) result. • < less than • <= less than or equal to • > greater than • >= greater than or equal to • Shift Operators • << left shift • >> right shift • module shift; • reg [1:0] start, result; • initial • begin • start = 1; • result = (start << 1); • end • endmodule

  9. Conditional Operators • Y = (A == b) ? A : B; • // This statement assigns A to Y if A and B are identical • // otherwise it assigns B to Y • wire [15:0] bus_a = drive_bus_a ? data : 16`bz; • // If drive_bus_a is 1, then bus_a = data • // If drive_bus_a is 0, then bus_a is high impedance. • data_out = (enable) ? temp : 32`bz;

  10. Verilog Model Example: A board with a display unit, a 16-bit counter and a clock generator • module binaryToESeg; • //Here we only display the E segment. • // A, B, C, D are registers to hold values for simulation • wire eSeg, p1, p2, p3, p4; • reg A, B, C, D; • nand #1 • g1 (p1, C, ~D), • g2 (p2, A, B), • g3 (p3, ~B, ~D), • g4 (p4, A, C), • g5 (eSeg, p1, p2, p3, p4); • endmodule

  11. module binaryToESegSim; • wire eSeg, p1, p2, p3, p4; • reg A, B, C, D; • nand #1 • g1 (p1, C, ~D), • g2 (p2, A, B), • g3 (p3, ~B, ~D), • g4 (p4, A, C), • g5 (eSeg, p1, p2, p3, p4); • initial // two slashes introduce a single line comment • begin • $monitor ($time,,, • "A = %b B = %b C = %b D = %b, eSeg = %b", • A, B, C, D, eSeg); • //waveform for simulating the binaryToESeg driver • #10 A = 0; B = 0; C = 0; D = 0; • #10 D = 1; • #10 C = 1; D = 0; • #10 $finish; • end • endmodule

  12. module binaryToESeg (eSeg, A, B, C, D); • output eSeg; • //eSeg is declared as an output port • input A, B, C, D; • // A, B, C, D are declared as input ports • nand #1 • g1 (p1, C, ~D), • g2 (p2, A, B), • g3 (p3, ~B, ~D), • g4 (p4, A, C), • g5 (eSeg, p1, p2, p3, p4); • endmodule

  13. module testBench; • wire w1, w2, w3, w4, w5; • binaryToESeg d (w1, w2, w3, w4, w5); • test_bToESeg t (w1, w2, w3, w4, w5); • endmodule • module binaryToESeg (eSeg, A, B, C, D); • input A, B, C, D; • output eSeg; • nand #1 • g1 (p1, C, ~D), • g2 (p2, A, B), • g3 (p3, ~B, ~D), • g4 (p4, A, C), • g5 (eSeg, p1, p2, p3, p4); • endmodule

  14. module test_bToESeg (eSeg, A, B, C, D); • input eSeg; • output A, B, C, D; • reg A, B, C, D; • initial // two slashes introduce a single line comment • begin • $monitor ($time,, • "A = %b B = %b C = %b D = %b, eSeg = %b", • A, B, C, D, eSeg); • //waveform for simulating the nand lip lop • #10 A = 0; B = 0; C = 0; D = 0; • #10 D = 1; • #10 C = 1; D = 0; • #10 $finish; • end • endmodule

  15. // A Verilog behavioral model • module binaryToESeg_Behavioral (eSeg, A, B, C, D); • output eSeg; • input A, B, C, D; • reg eSeg; • always @(A or B or C or D) begin • eSeg = 1; • if (~A & D) • eSeg = 0; • if (~A & B & ~C) • eSeg = 0; • if (~B & ~C & D) • eSeg = 0; • end • endmodule

  16. module m16 (ctr, clock); • output [3:0] ctr; • reg [3:0] value; • input clock; • always @(posedge clock) • ctr <= ctr + 1; • endmodule • module m555 (clock); • output clock; • reg clock; • initial • #5 clock = 1; • always • #50 clock = ~ clock; • endmodule

  17. module board; • wire [3:0] count; • wire clock, eSeg; • m16 counter (count, clock); • m555 clockGen (clock); • binaryToESeg disp (eSeg, count[3], count[2], count[1], count[0]); • initial • $monitor ($time,,,"count=%d, eSeg=%d", count, eSeg); • endmodule

  18. An Alternate Top-Level Module • module boardWithConcatenation; • wire clock, eSeg, w3, w2, w1, w0; • m16 counter ({w3, w2, w1, w0}, clock); • m555 clockGen (clock); • binaryToESeg disp (eSeg, w3, w2, w1, w0); • initial • $monitor ($time,,,"count=%d, eSeg=%d", {w3,w2,w1,w0}, eSeg); • endmodule

  19. Tying Behavioral and Structural Model Together • module counterToESeg (eSeg, clock); • output eSeg; • reg [3:0] value; • input clock; • initial • value = 0; • always @(posedge clock) • value <= value + 1; • nand #1 • g1 (p1, value[1], ~value[0]), • g2 (p2, value[3], value[2]), • g3 (p3, ~value[2], ~value[0]), • g4 (p4, value[3], value[1]), • g5 (eSeg, p1, p2, p3, p4); • endmodule

  20. module mixedUpESegDriver (eSeg, A, B, C, D); • output eSeg; • reg eSeg; • input A, B, C, D; • nand #1 • g1 (p1, C, D), • g2 (p2, A, ~B), • g3 (p3, ~B, ~D), • g4 (p4, A, C); • always @(p1 or p2 or p3 or p4) • eSeg = ~(p1 & p2 & p3 & p4); • endmodule

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