1 / 18

Paper By Brett Stanley Feero, and Partha Pratim Pande, Member IEEE Presentation by Bhavesh Makwana

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation IEEE Transaction on Computers, VOL. 58, NO.1. Paper By Brett Stanley Feero, and Partha Pratim Pande, Member IEEE Presentation by Bhavesh Makwana. Index Terms. NoC (Network on Chip). 3D Noc. Why?.

ringo
Download Presentation

Paper By Brett Stanley Feero, and Partha Pratim Pande, Member IEEE Presentation by Bhavesh Makwana

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Networks-on-Chip in a Three-Dimensional Environment: A Performance EvaluationIEEE Transaction on Computers, VOL. 58, NO.1 Paper By Brett Stanley Feero, and Partha Pratim Pande, Member IEEE Presentation by Bhavesh Makwana

  2. Index Terms NoC (Network on Chip) 3D Noc

  3. Why? • Limitations of 2D IP circuits. • Promises of 3D IP circuits.

  4. Organization • 3D NoC Architectures • Overview of 3D Arch. Evaluated. • Performance Analysis And Design Cost • Analysis of 3D Arch. & Standard Set of Matrics. • Experimental Results • Evaluation and Experimental Result Analysis.

  5. 1. 3D NoC Architectures 1.1 Mesh-Based Networks

  6. 1.2 Tree-Based Networks

  7. 2. Performance Analysis • Matrics used for Performance Analysis • Transport Mechanism • Wormhole Routing • Throughput • A metric to measure the rate at which message traffic can be sent across a communication fabric. • Latency • Refers to the length of time elapsed bet. The injection of a msg. header at source node and the reception of tail at the destination. • Energy • Energy dissipation across network due to transportation of msg and activities inside network switches. • Area • The amount of area used by an interconection network.

  8. 2.1 Performance Analysis in 3D Mesh-Based NoCs • Throughput • Principally related to two factors : number of physical links, average number of hops. For mash-based NoC no of links is defined as : In 8x8 2D Mesh NoC it yeilds 112 links. In 4x4x4 3D Mesh NoC it yeilds 144 links. For mash-based NoC no of hopes is defined as : In 8x8 2D Mesh NoC average hop counts is 5.33 In 4x4x4 3D Mesh NoC average hop counts is 3.81 With Decrease of hop counts increase in throughput is expected Contd.

  9. Energy • Depends on energy dissipated by the switch blocks & inter switch wire segments. • With more packets traversing the network, power will increase • The energy dissipated per flit per hope is given by • Latency • With lower hop count in 3D Arch decrease in latency is expected. Smaller hop counts, lower packet energy • Area • For 3D NoC area per switch increase with more ports in 3D NoCs. • In ciliated structure as no of switches reduces it reduces overall switch area.

  10. 3. Experimental Results • Experiment setup • Cycle-accurate network simulator used that can also simulate dTDMA buses. • Flit-driven and uses wormhole routing • In order to acquire energy and area characteristics, the n/w switches, dTDMA arbiter, and FIFO buffers were modeled in VHDL

  11. Experimental Results for various networks

  12. Conclusions • 3D Network structures provide a better performance compared to traditional 2D NoC architectures. • The mesh-based architectures show significant performance gains in terms of throughput, latency ad energy dissipation with small area overhead

More Related