A High Throughput Multi-channel Photon Counting Detector with Picosecond Timing

1. A High Throughput Multi-channel Photon Counting Detector with Picosecond Timing J.S. Lapington1, G.W. Fraser1, G.M. Miller1, T.J.R.Ashton1, P. Jarron2, M. Despeisse2, F. Powolny2, J. Howorth3, J. Milnes3, 1University of Leicester, 2CERN Microelectronics Group, 3Photek Ltd,

2. HiContent Project • “A Scaled-up High Content Photon-Counting Detector for Life Science Applications” • Three year STFC PIPSS project • Leicester, CERN, Photek, Manchester, GCI • Spin out technologies from Space and Particle Physics • MCP detector design, image readouts, multi-channel ASIC electronics • Applications requiring: • Photon counting • Picosecond event timing • Parallel multi-channel acquisition • High throughput J S Lapington – PSD8 – Glasgow

3. Applications • The ‘omics – particularly Proteomics • The study of protein interactions in vivo • Time resolved spectroscopies • Fluorescence lifetime imaging • Fluorescence correlation spectroscopy • Plus others e.g. Raman, polarization anisotropy, dielectric, etc. • Other applications: • Optical tomography, etc. J S Lapington – PSD8 – Glasgow

4. Detector Specifications • Detector format: 25 mm and 40 mm diameter • Multi-channel parallel event acquisition • Up to 1024 channels – using CERN NINO ASIC • Discrete pixel format: 8 × 8, 16× 16, up to 32 × 32 • High event time resolution • Small pore MCPs – 80 ps pulse rise time • 20 ps goal using CERN HPTDC ASIC • Counting rates • Maximum event rate/ch - 10 Mcounts/sec • ~100 Mcount/s total (MCP limited) • Highly flexible and economic • Channel grouping for simultaneous acquisition • <1% of the cost per channel c.f. current devices J S Lapington – PSD8 – Glasgow

5. Detector Schematic Photon Window Photocathode Photoelectron MCP electron gain MCP stack Current collected on readout electrode Electrode array ASIC preamp and discriminator timesphoton event Readout electronics: PCB with ASIC electronics underside TDC + FPGA processing LVDS logic out J S Lapington – PSD8 – Glasgow

6. Compact Detector Envelope 25 mm Vacuumenclosure ~20 mm Multi-layer ceramic Electronics on coupled PCBoutside vacuum 8 x 8 array of independent 20 ps channels J S Lapington – PSD8 – Glasgow

7. Prototype Tube Design J S Lapington – PSD8 – Glasgow

8. Multi-layer ceramic design Designed and manufactured at CERN J S Lapington – PSD8 – Glasgow

9. Multi-layer ceramic anode Inside surface (anode pixel array) Outside surface (interface with electronics) J S Lapington – PSD8 – Glasgow

10. Small pore MCP risetime 3 micron pore MCPs manufactured by Photonis 80 ps pulse rise-time 140 ps pulse length Data courtesy of J S Lapington – PSD8 – Glasgow

11. NINO amplifier-discriminator NINO ASIC developed by CERN J S Lapington – PSD8 – Glasgow

12. 64 Channel Prototype PCB NINO ASIC 120 mm J S Lapington – PSD8 – Glasgow

13. Prototype PCB Test Configuration J S Lapington – PSD8 – Glasgow

14. Prototype PCB Test Results Pulse width measurement vs. input charge for the 6 chips tested Time walk measurements vs. pulse width for the 6 chips tested Time jitter vs. charge for the 16 test channels of2 PCBs. Diamonds show the leading edge time jitter. Squares show the time jitter in the absolute event timing after time walk correction Temperature evolution of a circuit after power switched on at t=0 J S Lapington – PSD8 – Glasgow

15. Event Timing • Goal: 20ps event timing • Using CERN-developed HPTDC ASIC • Initial tests with 64 ch prototype using CAEN V1290A • VME module • 32 channels at 25ps • HPTDC development board • Manufactured • Under test CAEN V1290A HPTDC Test Board J S Lapington – PSD8 – Glasgow

16. Initial tests with the HPTDC J S Lapington – PSD8 – Glasgow

17. Preliminary results J S Lapington – PSD8 – Glasgow

18. Layout of the 32 channel NINO J S Lapington – PSD8 – Glasgow

19. Time Jitter Measurements J S Lapington – PSD8 – Glasgow

20. 32 Channel NINO Noise Study J S Lapington – PSD8 – Glasgow

21. 256 Channel Mechanical Layout J S Lapington – PSD8 – Glasgow

22. Summary of Current Status • 8 x 8 Pixel2 Prototype • 64 channel front-end electronics manufactured & tested • 64 channel multilayer ceramic manufactured & tested • Detector designed and manufacture in progress • 32 channel VME HPTDC procured - system being characterized • Prototype field trials expected 4th quarter 2008 • 16 x 16 Pixel2 HiContent final design • Change to 40 mm detector format to maximize throughput • In-house HPTDC development board under test • 64 channel HPTDC daughterboard design started • 32 channel low power NINO mk3 chip designed and manufactured • 256 channel system design under development • Passive front-end header PCB with detector interface • 4 x 64 channel plug-in daughter-boards (preamp + TDC) • Back-end PCB for control and digital processing (FPGA/processor/USB) J S Lapington – PSD8 – Glasgow

23. IRPICS Follow-on Project • “Information Rich Photon Imaging of Cells” • Expansion of HiContent detector concept • BBSRC funded, 3 year, TDRI project • Collaborators: Manchester, Leicester, CERN • Specification and performance • 32 × 32 pixel2 readout • 1024 readout channels • 20 ps event timing • Max event rate/channel - 10 Mcounts/sec • ~100 Mcount/s total (limited by current MCP technology) • FPGA-based intelligent digital processing J S Lapington – PSD8 – Glasgow