Instructor: Dr. Phillip Jones (phjones@iastate) Reconfigurable Computing Laboratory

1. ECpE 583Reconfigurable ComputingLecture 21: Thur 11/6/2008(Placing Applications onto FPGAs: Part II) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://www.ece.iastate.edu http://class.ece.iastate.edu/cpre583 (coming soon) http://www.arl.wustl.edu/~phjones/cpre583 (temporary)

2. Class Announcements • Updated schedule (coming soon) • MP2 concerns

3. Outline • Placing an application on an FPGA • Low-level details • Today we will focus on routing

4. Applications on FPGA • Low-level: Application to FPGA refs • Reconfigurable Computing (2008) • Scott Hauck, Andre DeHon • The VLSI handbook (2000) • Wai-Kai Chen (note: there’s a 2nd edition (2006)) • Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays • Jason Cong (TODAES’96)

5. Applications on FPGA: Low-level • Implement circuit in VHDL (Verilog) • Simulate compiled VHDL • Synthesis VHDL into a device independent format • Map device independent format to device specific resources • Check that device has enough resources for the design • Place resources onto physical device locations • Route (connect) resources together • Completely routed • Circuit meets specified performance • Download configuration file (bit-steam) to the FPGA

6. Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

7. Route • Connect placed resources together • Two requirements • Design must be completely routed • Routed design meets timing requirements • Widely used algorithm “PathFinder” • PathFinder (FPGA’95) • McMurchie and Ebeling • Reconfigurable Computing (Chapter 17) • Scott Hauch, Andre Dehon (2008)

8. Route: Route FPGA Circuit • FPGA editor screen shot.

9. Route (PathFinder) • PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs (FPGA’95) • Basic PathFinder algorithm • Based closely on Djikstra’s shortest path • Weights are assigned to nodes instead of edges

10. Route (PathFinder): Example • G = (V,E) • Vertices V: set of nodes (wires) • Simple node cost cn = bn • Edges E: set of switches used to connect wires S1 S2 S3 2 3 1 4 3 1 1 A B C 1 1 3 4 1 3 2 D1 D2 D3

11. Route (PathFinder): Example • Simple node cost cn = bn • Obstacle avoidance • Note order matters, must start with 2 to get a solution S1 S2 S3 2 3 1 4 3 1 1 A B C 1 1 3 4 1 3 2 D1 D2 D3

12. Route (PathFinder): Example • cn = b * p • p: sharing cost (function of number of signals sharing a resource) • Congestion avoidance S1 S2 S3 2 3 1 4 3 1 1 A B C 1 1 3 4 1 3 2 D1 D2 D3

13. Route (PathFinder): Example • cn = (b + h) * p • h: history of previous iteration sharing cost • Congestion avoidance S1 S2 S3 2 1 1 2 1 A B C 1 2 1 1 2 D1 D2 D3

14. Next Lecture • Finish Placing Applications on FPGAs • Compute Models: Part I • Recommended Reading • Design Patterns for Reconfigurable Computing • http://ic.ese.upenn.edu/abstracts/despat_fccm2004.html

15. Questions/Comments/Concerns • Write down • Main point of lecture • One thing that’s still not quite clear • If everything is clear, then give an example of how to apply something from lecture OR