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Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, and Tsai-Wen Cheng

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, and Tsai-Wen Cheng. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 16, May 2008, Page(s):594 - 598.

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Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, and Tsai-Wen Cheng

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  1. A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, and Tsai-Wen Cheng Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 16, May 2008, Page(s):594 - 598 Adviser : Kai-Cheng Wei Postgraduate : Chiuan-Tai Xiao Number : 96662011 Date : 2008.11.24 National Changhua University of Education Graduate Institute of Integrated Circuit Design

  2. Outline • Abstract • Low-power high-speed 8-bit CLA • Simulations and implementation • Conclusion

  3. Abstract • A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-Vt domino logic blocks which are arranged in a PLA-like design style with pipelining is presented. • The modified domino logic circuits employ dual-Vt transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. • The proposed dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.

  4. Low-power high-speed 8-bit CLA a. Typical dual-Vt domino logic circuits precharge phase evaluation phase 1 0 0 1

  5. Typical two-stage dual-Vt domino logic circuit to construct a pipeline structure

  6. b. Modified dual-Vt domino logic circuits

  7. c. High-Vt transistor with reverse-biased bulk-source voltage In the simulation, Vdd=1.8V, VB=3V, T=25 C.

  8. d. PLA-styled 8-bit CLA design(1) NOT-OR plane Ci+1 = Gi + Pi ● Ci Pi = Ai xor Bi Gi=Ai ● Bi

  9. d. PLA-styled 8-bit CLA design(2)

  10. e. Cycle-based operation and area analysis An 8-bit adder using our proposed design, the overall transistor count is 882.

  11. Simulations and implementation(1) • To reveal the power-saving advantage of the proposed low power design, two 8-bit CLAs are, respectively, implemented by the modified single-Vt domino logic and the modified dual-Vt domino logic using the same CMOS process. • The two CLAs implemented by TSMC 0.18-µm 1P6M CMOS process.

  12. Simulations and implementation(2)

  13. Simulations and implementation(3)

  14. Simulations and implementation(4)

  15. Conclusion • We propose a low-power high-speed PLA-styled dual-Vt domino logic design for adder implementation. • A modified dual-Vt domino logic circuit is used for pipelining structure and the unnecessary power consumption is avoided. • Not only is the correctness of the function in the gigahertz range preserved, the power dissipation is also reduced. • The PLA-styled dual-Vt domino logic structure using only one clock makes the result of an 8-bit adder appear in two cycles.

  16. Thanks for your attention.

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