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NETOS5.1 Training

NETOS5.1 Training. NS7520 Overview NETOS5.1 Overview BSP Changes BSP & Board Configurations Build File Changes for GHS Makefile Changes for GNU Linker Files. NS7520 Overview. No Cache No Port B No Parallel Ports, No ENI Less GPIO, only Port A and Port C

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NETOS5.1 Training

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  1. NETOS5.1 Training • NS7520 Overview • NETOS5.1 Overview • BSP Changes • BSP & Board Configurations • Build File Changes for GHS • Makefile Changes for GNU • Linker Files

  2. NS7520 Overview • No Cache • No Port B • No Parallel Ports, No ENI • Less GPIO, only Port A and Port C • Register address changes in Ethernet module • Some bits changes in eth & spi registers

  3. NETOS5.1 Overview • NETOS5.1 ONLY Support NS7520 • Boot Loader • BSP Restructure • Ethernet Driver • Image Build File Changes

  4. BSP Changes • BSP Restructure 1. Files in /src/bsp/customize MUST BE CUSTOMIZED FOR YOUR PARTICULAR HARDWARE: cs.c -- sets up the NET+ARM chip selects gpio.c -- sets up the GPIO ports led.h -- defines used by the LED driver errhndlr.c -- contains error handling routines pll.s -- contains a list of PLL settings, indexed by chip reversion ID 2. Ncc_post() is called from main(), romstart.c does not exist anymore. 3. Decompress() is called from bootloader, Set R14 in UNDEF mode to 0xff808421 to signal a software restart. 4. In init.s, Put the DMA controller into Test mode. This will let us use its internal registers as scratch pad memory to call ncc_init(). 5. In ncc_init(), memory section “initdata” is used to store power on information: customizeReadPowerOnButtons(chipType, initdata) 6. In ncc_init(), memory section “nccdata” is used to store “debugger” & “software reset” flags.

  5. BSP Changes • Settings.c. Entries have been added for chip ID 40 (NS7520-0), chip ID 41 (NS7520-1) and possible future chip ID 42. NOTE: 7520-0 can only use external oscillator. @55MHZ, cs0WaitStates has to be 5, cs1SdWaitStates has to be 1 for the parts on our development board. 7520-1 can use external oscillator or PLL+crystal. @55MHZ, cs0WaitStates has to be 5, cs1SdWaitStates has to be 1 for the parts on our development board. If 7520-1 use PLL+crystal, bspconf.h need to be changed, and some jumpers and resistors need to be installed on the board. Please consult Don Stone on which jumpers need to be installed and what values cs0WaitStates and cs1SdWaitStates should be @55MHZ, @46MHZ and @36MHZ

  6. BSP Changes • PLL & sysClock.c NOTE: The PLLCNT field in PLL control register is initialized on hardware reset as a function of the input seen on ADDR. NETOS5.1 BSP does not write to this field. Writing the register when the PLL is enabled produces a hardware reset to allow for settling of the new PLL setting. If PLL is enabled, sysClockFrequency is calculated using the fields “IS”, “FS” and “ND” in PLL settings register, not the “PLLCNT” field in PLL control register. If PLL is enabled, the internal auxiliary clock signal (XTAL) Frequency is always (CRYSTAL_OSCILLATOR_FREQUENCY/5) regardless what the sysClockFrequency is, 55Mhz, 46Mhz or 36Mhz.

  7. BSP Changes • Serial Driver • SPI Driver • HDLC Driver

  8. BSP & Board Configurations • Default configurations: … #define BSP_INCLUDE_SERIAL_DRIVER_1 1 #define BSP_USE_FLASH_FOR_NVRAM #define BSP_BOOTLOADER_SIZE (64*1024) #define BSP_APPLICATION_OFFSET BSP_BOOTLOADER_SIZE #define BSP_APPLICATION_ADDRESS (BSP_APPLICATION_OFFSET + BSP_ROM_BASE) #define BSP_APPLICATION_IMAGE_SIZE 0xd0000 #define CLOCK_SOURCE 0 /*0 =SELECT_THE_XTAL1_INPUT*/ …

  9. BSP & Board Configurations • To enable serial port 2 #define BSP_INCLUDE_SERIAL_DRIVER_2 1 Jumper JP6 is “OUT” NOTE: DCD, DSR and RI are not connected to “PORTB” on the board.

  10. BSP & Board Configurations • To enable SPI port 2 /* #define BSP_INCLUDE_SERIAL_DRIVER_2 1 */ #ifndef BSP_INCLUDE_SERIAL_DRIVER_2 /* If we do not have an RS-232 driver, we can include SPI driver */ #define BSP_INCLUDE_SPI_DRIVE_2 1 #endif Jumper JP6 is “IN” Example application in /src/examples/naspi can now access EEPROM at U30 on the board through SPI interface.

  11. BSP & Board Configurations • To enable PLL for NS7520-1 #define CLOCK_SOURCE 1 /*0 = SELECT_THE_XTAL1_INPUT*/ Resistor changes on the board, you need soldering gun! JP54 is “IN” For 55Mhz, jumpers JP46-JP53 are “OUT” For 46Mhz, JP52 is “IN”, others are “OUT” For 36Mhz, JP50 & JP51 are “IN”, others are “OUT” wait states for CS0 and CS1? Ask Don Stone.

  12. BSP & Board Configurations • If #define BSP_USE_FLASH_FOR_NVRAM, rom.bin does not boot Why not use bootloader and image.bin? if you have to use rom.bin: /* #define BSP_USE_FLASH_FOR_NVRAM */ /* This is for 20UM board if BSP_USE_GPIO_DRIVE_NVRAM is defined, PORTC0, PORTC4, PORTC7, PORTC3 will be used to drive NVRAM.*/ #define BSP_USE_GPIO_DRIVE_NVRAM JP6 has to be “IN”

  13. Build File Changes for GHS • Debug.bld and romzip.bld are gone • Image.bld will build debugger image and image.bin to use with bootloader • Please note that debugger image and unzipped application code start at the same location • Rom.bld is still there, better not use it

  14. Makefile Changes for GNU • No longer overwrite libc.a and crt0.o in cygwin directory • NETOS5.1 use libc.a and crt0.o in /netos/lib/32b/gnu/ directory • You must use the Makefile in our examples directory as template for your application • In the Makefile NETOS_CLIBPATH=./../../../../lib/32b/gnu NETOS_STARTFILE=$(NETOS_CLIBPATH)/crt0.o LINKOPT= -mbig-endian –nostartfiles NETOS_LIBS= -L $(NETOS_LIBPATH) -L $(NETOS_CLIBPATH) $(DEBUG_VERSION): $(OBJECTS) $(LINK_CMD) $(LIBS) $(CC) -o $(DEBUG_VERSION) $(OBJECTS) $(LINKOPT) -T $(LINK_CMD) $(NETOS_STARTFILE) $(NETOS_LIBS) -Wl,-Map,$(MAPFILE) $(NM) -n $(DEBUG_VERSION) > $(SYMFILE) For C++ application NETOS_STARTFILE=$(NETOS_CLIBPATH)/crt0.o $(NETOS_CLIBPATH)/crtbegin.o $(NETOS_CLIBPATH)/crtend.o

  15. Linker Files • One linker file set for all applications • In netos/src/linkerScripts This directory contains linker scripts and configuration files that are shared by all applications. These files are: bootldr.dat bootloader configuration file used to generate the file image.bin. It controls the information placed in the bootloader header of the image. image.ld GNU linker script used to build an image that can be debugged and used with the bootloader. image.lx Green Hills linker script used to build an image that can be debugged and used with the bootloader. rom.ld GNU linker script used to build an image that will run from ROM. The bootloader is not used with this type of image. rom.lx Green Hills linker script used to build an image that will run from ROM. The bootloader is not used with this type of image. Except: nahttp & namail examples use local rom.ld and image.ld for GNU

  16. References • BSP Porting Guide for GHS & GNU • Getting Started with GHS and GNU • NS7520 Hardware Manual

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