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The Design Of A Differential CMOS Charge Pump For High Performance Phase-Locked-Loops. 班級:積體所碩一 學生:林欣緯 指導教授:林志明 教授. Bortecene Terlemez and John P. Uyemura ISCAS2004. Outline. Introduction Charge Pump Architecture Simulation Results PLL Test Result Conclusion. Introduction.
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The Design Of A Differential CMOS Charge Pump For High Performance Phase-Locked-Loops 班級:積體所碩一 學生:林欣緯 指導教授:林志明 教授 Bortecene Terlemez and John P. Uyemura ISCAS2004
Outline • Introduction • Charge Pump Architecture • Simulation Results • PLL Test Result • Conclusion
Introduction • Fundamentally, an ideal charge pump combined with an ideal PFD provides an unbounded pull-in range (limited by the oscillator’s frequency range) and zero static phase error in charge pump PLLs.
The requirements for an effective charge pump • Equal charge/discharge current at any charge pump output voltage. • Minimal charge injection into the output node. • Minimal charge sharing between the output node and any floating node.
Improved single ended charge pump circuit get rid of floating nodes to remove the charge-sharing problem
Charge pump outputlinear range 1.07 V/output
Conclusion • achieve low charge sharing and low charge injection in low voltage PLL applications. • the output voltage range of the charge pump is increased while charging/discarging current matching is realized.