NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER

1. NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER Design and implementation of a Multimedia Extension for a RISC Processor Eduardo Jonathan Martínez Montes Prof. Marco Antonio Ramírez Salinas IPN-CIC MICROSE Lab

2. OUTLINE • Background • Motivation • Multimedia applications • State of the art • Problem Description • Overview • SISD • SIMD • SISD vs SIMD • Saturation arithmetic • Example • Instruction format • Objective • Main objective • Specific objectives • Hypothesis • Multimedia support • MDMX • Vector to vector arithmetic • Technical Merits • Data path • Vector units IPN-CIC MICROSE Lab 2

3. BACKGROUND Motivation Lagartois a superscalar embedded processor, now in develop by the HPC research team of CIC-IPN. The goal of this effort is to be used to help in the research and teaching. This processor require the design and build many blocks, so that, this project is part of a bigger project. IPN-CIC MICROSE Lab 3

4. BACKGROUND Motivation (cont.) IPN-CIC MICROSE Lab 4

5. BACKGROUND Motivation (cont.) IPN-CIC MICROSE Lab 5

6. BACKGROUND Multimedia applications Photo edition Video edition Rendering Video games IPN-CIC MICROSE Lab 6

7. BACKGROUND State of the art AltiVec - IBM 1996 2002 SSE4 - Intel Pentium II (MMX)- Intel 2006 Sandy Bridge y Bulldozer - Intel y AMD 1998 3DNow!. - AMD SSE3 - Intel 2000 2004 2011 1996 1998 2000 2002 2004 2006 2008 2010 2012 2002 2008 2013 1997 SSE2 - Intel Advanced Vector Extensions (AVX) - Intel AVX2 - Intel AltiVec - Motorola 2004 1999 SSE y SSE2 - AMD Streaming SIMD Extensions (SSE)- Intel 1996 2003 Advance 3DNow! (3DNow! 2) - AMD IPN-CIC MICROSE Lab 7

8. PROBLEM DESCRIPTION Overview Multimedia Extension is a vector machine that is embedded in situ with the main Superscalar Processor, it is used for deal with multimedia applications. Main processor Multimedia extension Lagarto processor IPN-CIC MICROSE Lab 8

9. PROBLEM DESCRIPTION SISD Single Instruction Single Data is a term referring to a computer architecture In which a single processor executes a single instruction stream. IPN-CIC MICROSE Lab 9

10. PROBLEM DESCRIPTION SIMD Single Instruction Multiple Data is a class of parallel computer. It describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously. These machines exploit data level parallelism. IPN-CIC MICROSE Lab 10

11. PROBLEM DESCRIPTION SISD vs SIMD IPN-CIC MICROSE Lab 11

12. PROBLEM DESCRIPTION Saturation arithmetic It is a version of arithmetic in which all operations such as addition and multiplication are limited to a fixed range between a minimum and a maximum value. If the result of an operation is greater than the maximum, it is set to the maximum. On the other hand, if it is below the minimum, it is clamped to the minimum value. 50+80=130 150 + 170 = 255 120-135=0 IPN-CIC MICROSE Lab 12

13. PROBLEM DESCRIPTION Example Example: get negative image IPN-CIC MICROSE Lab 13

14. PROBLEM DESCRIPTION Example (cont.) SISD Processing IPN-CIC MICROSE Lab 14

15. PROBLEM DESCRIPTION Example (cont.) SIMD Processing IPN-CIC MICROSE Lab 15

16. HYPOTESIS Instruction format Co-processor instruction COP1=010001 COP2=010010 IPN-CIC MICROSE Lab 16

17. HYPOTESIS Instruction format (cont.) Data format and item chooser IPN-CIC MICROSE Lab 17

18. HYPOTESIS Instruction format (cont.) Source 1 Source 2 Destination IPN-CIC MICROSE Lab 18

19. HYPOTESIS Instruction format (cont.) IPN-CIC MICROSE Lab 19

20. OBJECTIVE Objectives • General Objective • Design a multimedia extension unit for a RISC processor (Lagarto). • Specific Objectives • Design a vector adder w/wo saturation arithmetic. • Design a multiplier w/wo saturation arithmetic. • Implement the complete Instruction set of the MIPS Digital Media extension (MDMX). IPN-CIC MICROSE Lab 20

21. HYPOTESIS MIPS Digital Media Extension • Lagarto II processor with: • MDMX supports video, audio, and graphics pixel processing. • MDMX is not part of the MIPS Instruction Set. • A processor that implements the MDMX must implement the MIPS-V ISA • MIPS MDMX is not intended for general purpose computing. • Software support is via shared libraries and assembly language only. IPN-CIC MICROSE Lab 21

22. HYPOTESIS MIPS Digital Media Extensión (cont.) • MDMX shares a register file with the Floating Point Unit. • Data is moved between the shared register file and memory with existing Floating Point Load and Store double operations. • Registers are interpreted in two formats: Quad Half and Oct Byte format. • MDMX also shared the 8 Floating Point Condition Code bites. • MDMX has a private 192 bit accumulator register. IPN-CIC MICROSE Lab 22

23. HYPOTESIS Vector to vector arithmetic IPN-CIC MICROSE Lab 23

24. TECHNICAL MERITS Data path IPN-CIC MICROSE Lab 24

25. TECHNICAL MERITS Vector units • Vector adder w/wo saturation arithmetic. • Vector subs tractor w/wo out saturation arithmetic. • Vector multiplier w/wo out saturation arithmetic. • Instruction vector Queue. • Vector Load/Store Queue. IPN-CIC MICROSE Lab 25

26. Q&A IPN-CIC MICROSE Lab 26