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Computer Architecture

This outline explains the disadvantages of single-cycle implementation in computer architecture and introduces the concept of multi-cycle implementation, which improves hardware utilization and reduces cycle time.

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Computer Architecture

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  1. Computer Architecture Multi-cycle Implementation

  2. Outline • Disadvantagesof the Single-cycle implementation • Long cycle time, too long for all instructions except for the slowest (lw instruction) • Inefficient hardware utilization with unnecessarily duplicated resources • Multi-cycle implementation • Partition execution into small steps • Process each step in one cycle • Different numbers of cycles for different instructions • Example • R-format instruction (4 cycles): (1) Instruction fetch (2) Instruction decode/register fetch (3) ALU operation (4) Register write • Load instruction (5 cycles): (1) Instruction fetch (2) Instruction decode/register fetch (3) address computation (4) memory read (5) Register write

  3. Multiple-cycle Concept • Reduce resource requirements by using the same resource for different purposes during different cycles • Single memory unit for instructions and data • Single ALU • Use temporary registers to store intermediate results during execution • Instruction register (IR), A register, B register, ALUOut register, Memory data register (MDR) • Partition criteria: at most one of the following operations • Memory access • Register file access • ALU operation

  4. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Multiple-cycle Datapath

  5. Overview of Multi-cycle Execution

  6. Instruction Fetch Step

  7. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Instruction Fetch Step

  8. Instruction Decode/Register Fetch Step

  9. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Instruction Decode/Register Fetch Step

  10. R-format Execution Step

  11. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 R-format Execution Step

  12. R-format Completion Step

  13. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 R-format Completion Step

  14. Load/Store Address Computation Step

  15. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Load/Store Address Computation Step

  16. Load Memory Access Step

  17. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Load Memory Access Step

  18. Load Completion Step

  19. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Load Completion Step

  20. Store Memory Access Step

  21. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Store Memory Access Step

  22. Branch Completion Step

  23. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Branch Completion Step

  24. Jump Completion Step

  25. 0 M U X Jump address[31-0] 26 28 1 Instruction[25-0] Shift left 2 2 Instruction [31-26] PC[31-28] Instruction [25-21] PC 0MUX1 Read register1 0MUX1 Read data 1 A Address Instruction [20-16] Read register2 Zero memory ALUOut 0MUX1 ALU ALU result Read data 2 Instruction [15-0] Write register MemData B 0 Instruction [15-11] M U X 4 Instruction register 1 Write data Registers Write 2 data 3 Instruction [15-0] 0MUX1 Memory Data Register Sign extend 16 32 Shift left 2 Jump Completion Step

  26. Summary of Multi-cycle Steps

  27. CPI of the Multi-cycle Implementation • Number of clock cycles • Loads : 5 • Stores : 4 • R-format instructions : 4 • Branches : 3 • Jumps : 3 • Instruction mix • 22% loads, 11% stores, 49% R-format instructions, 16% branches, and 2% jumps • CPI = 0.22 x 5 + 0.11 x 4 + 0.49 x 4 + 0.16 x 3 + 0.02 x 3 = 4.04

  28. Multiple-cycle Implementation (with control signals added)

  29. Next state Next-state function Current state Clock Inputs Output function Outputs Finite State Machine • Finite state machine • There are a finite set of possible machine states • The machine has two functions • next state function dependent on current state and input values • output function dependent on current state and input values • Two kinds of state machines • Moore machine has output based only on current state • Mealy machine has output based on current state and input values • We use a Moore machine

  30. High-Level Control Flow • Common 2-clock sequence to fetch/decode any instruction • Separate sequence of 1 to 3 clocks to execute specific types of instruction

  31. I n s t r u c t i o n d e c o d e / I n s t r u c t i o n f e t c h r e g i s t e r f e t c h 0 M e m R e a d 1 A L U S r c A = 0 I o r D = 0 A L U S r c A = 0 I R W r i t e A L U S r c B = 1 1 S t a r t A L U S r c B = 0 1 A L U O p = 0 0 A L U O p = 0 0 P C W r i t e ) P C S o u r c e = 0 0 ) ' e Q ) p ' y t E - J R ' B = ' = p = O ( ) p ' p W M e m o r y a d d r e s s S O ' O = B r a n c h ( p J u m p ( O ( c o m p u t a t i o n r o E x e c u t i o n c o m p l e t i o n ) ' c o m p l e t i o n W L ' = p O ( 2 6 8 9 A L U S r c A = 1 A L U S r c A = 1 A L U S r c B = 0 0 A L U S r c A = 1 P C W r i t e A L U S r c B = 1 0 A L U O p = 0 1 A L U S r c B = 0 0 P C S o u r c e = 1 0 A L U O p = 0 0 P C W r i t e C o n d A L U O p = 1 0 P C S o u r c e = 0 1 ( ) O ' p W = L ' ' S = W ' ) p O M e m o r y M e m o r y ( a c c e s s a c c e s s R - t y p e c o m p l e t i o n 3 5 7 R e g D s t = 1 M e m R e a d M e m W r i t e R e g W r i t e I o r D = 1 I o r D = 1 M e m t o R e g = 0 W r i t e - b a c k s t e p 4 R e g D s t = 0 R e g W r i t e M e m t o R e g = 1 Finite State Machine Diagram

  32. Finite State Machine Controller

  33. PLA Implementation AND Plane • Outputs and next state are calculated by sum of products of inputs and current state • Columns in AND plane form products • one column per unique product term • Rows in OR plane form sum • Programmed by placing transistors at intersection of row and column according to logic function • When the inputs are fully decoded (2N columns), a PLA is logically equivalent to a ROM • Optimization can be automated OR Plane

  34. Exceptions and Interrupts • Exception: an unexpected event from within the processor that traps into an operating system service routine • Arithmetic overflow • Undefined instruction • System call • Interrupt: an event that comes from outside of the processor that also traps into an operating system service routine • I/O device request (I/O completion) • Handling of exceptions and interrupts in MIPS • Saves PC (the address of the offending instruction) in EPC (exception program counter) • Records the reason for the exception or interrupt in the CAUSE register • Jumps to the operating system service routine • rfe (return from exception) instruction restores the PC from EPC

  35. Single-cycle implementation Clock cycle time Pipelined implementation (next class) Multi-cycle implementation CPI Summary • Disadvantages of the Single-cycle implementation • Long cycle time, too long for all instructions except for the slowest • Inefficient hardware utilization with unnecessarily duplicated resources • Multiple-cycle implementation • Partition execution into small steps of comparable duration • Process each step in one cycle • Three general forms of control implementation • Random logic • PLA • Microcode

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