FaridehShiran Department of Electronics Carleton University, Ottawa, ON, Canada

1. SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors FaridehShiran Department of Electronics Carleton University, Ottawa, ON, Canada fshiran@doe.carleton.ca

2. Outline • Introduction • First Generation 90 nm • Second Generation 65 nm • Third Generation 45 nm • Design Methodology and Automation • Low Power Standard: IEEE-1801 • Conclusion

3. Outline • Introduction • First Generation 90 nm • Second Generation 65 nm • Third Generation 45 nm • Design Methodology and Automation • Low Power Standard: IEEE-1801 • Conclusion

4. Introduction • Demand for increasing features of handheld devices • Processors speeds reaching 1 GHz and above • Bottleneck: battery technology • Trade-off: battery life versus higher speeds • Technology Scaling • Advantages • Disadvantagrs

5. Demand for Increased Mobile Product Features and Performance

6. Leakage Power in different technologies • Extend battery life • Co-optimization: Process and circuit • Texas Instruments (TI) for 90 nm, 65 nm, 45 nm • SmartReflex

7. Outline • Introduction • First Generation 90 nm • Second Generation 65 nm • Third Generation 45 nm • Design Methodology and Automation • Low Power Standard: IEEE-1801 • Conclusion

8. 90 nm Leakage Power Management • Exponential increase in leakage : • Power gating • uses high Vt sleep transistors which cut off VDD from a circuit block • SRAM retention • Losing data stored in SRAM, retention needed • Multiple channel length • Reducing leakage power both in active and idle modes • OMAP2 Mobile Application Process • Integrate above techniques in a 90 nm technology

9. Power gating Global/local power grid methodology

10. Outline • Introduction • First Generation 90 nm • Second Generation 65 nm • Third Generation 45 nm • Design Methodology and Automation • Low Power Standard: IEEE-1801 • Conclusion

11. 65nm Power and Performance • Larger increase in device leakage • Improving SmartReflex power management toolbox: • Leakage power management • aggressive dynamic voltage frequency scaling • Process and temperature adaptive voltage scaling 65 nm technology OMAP3430 application processor

12. Outline • Introduction • First Generation 90 nm • Second Generation 65 nm • Third Generation 45 nm • Design Methodology and Automation • Low Power Standard: IEEE-1801 • Conclusion

13. 45 nm Power and Performance • Further reduction of active leakage power and performance increase • Adaptive body bias (ABB): • FBB • RBB • Retention Til Access (RTA) • Full power state • Low power state • Single Chip 3.5 Baseband and Applications Processor • Integrate above techniques in a 45 nm technology

15. Outline • Introduction • First Generation 90 nm • Second Generation 65 nm • Third Generation 45 nm • Design Methodology and Automation • Low Power Standard: IEEE-1801 • Conclusion

16. Design methodology and automation • SmartReflex-PriMer (SmartPriMer): • Chip-level leakage management design methodology • Power Managed (PM) modules • Power-Aware Verification • PM integrity check • Power-aware simulations at RTL and gate levels • Not power-aware • Power-aware

18. Outline • Introduction • First Generation 90 nm • Second Generation 65 nm • Third Generation 45 nm • Design Methodology and Automation • Low Power Standard: IEEE-1801 • Conclusion and Future Work

19. Low Power Standard: IEEE-1801 • Unified Power Format (UPF): • Why UPF? • PM intent information • UPF1.0: power design intent in verification and implementation • Power states • Power domain specifications • Retention, Isolation and level shifting • UPF2.0-IEEE1801 • Command layering • Supply set handles

20. Conclusions • For higher performance (power management) • Three generation technologies • 90nm, 65nm, 40nm • design methodology • SmartReflex-PriMer • Power-Aware Verification • Standard • UPF 1.0 • UPF 2.0

21. Thank You