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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices. Three-state devices Multiplexers. Three State Buffers/Drivers. A buffer/inverter with enable input
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ECE 3110: Introduction to Digital SystemsChapter 6Combinational Logic Design Practices Three-state devices Multiplexers
Three State Buffers/Drivers • A buffer/inverter with enable input • Buffer Buffer Inverter Inverter Active High Enable Active Low Enable Active High Enable Active Low Enable • The device behaves like an ordinary buffer/inverter when the enable input is asserted. • The output is floating ( High Impedance, Hi-Z ) when the enable input is deasserted ( The input is isolated from the output, behaves as if it did not exist) • Application: Controlling the access of a single line/bus by multiple devices
Three-state buffers • Output = LOW, HIGH, or Hi-Z. • Can tie multiple outputs together, if at most one at a time is driven.
Standard SSI/MSI 3-state buffers SSI: 74x125, 74x126 (independent enable inputs) MSI: 74x541 and varieties such as 74x540, 74x240, 74x241
Octal non-inverting 3-state buffer Hysteresis
Three-state transceiver • Pairs of 3-state buffers connected in opposite directions between each pair of pins, so data can be transferred in either direction. • DIR determines the direction of transfer (A-->B or B-->A)
Transceiver application Bidirectional buses
Multiplexers (Mux) E.g. Put between Processor’s registers and ALU A 16-bit processor where 3-bit field specifies one of 8 registers. The 3-bit field is connected to the select inputs of an 8-input, 16-bit Mux. Select one of n sources of data to transmit on a bus.
Other multiplexer varieties • 2-input, 4-bit-wide • 74x157 • 4-input, 2-bit-wide • 74x153
Expanding Multiplexers 32-to-1 Mux
Demultiplexers • A Mux is used to select one of n sources of data to transmit on a bus. • A demultiplexer can be used to route the bus data to one of m destinations. Just the inverse of a mux. • A binary decoder with an enable input can be used as a Demux. E.g. 74x139 can be used as a 2-bit, 4-output Demux.
Homework #8 (Due: 04/09/2007 ) • Notes: On all timing calculation problems, describe the circuit path used and show each number in the calculation. • Eg. Twct=T1+T2 • T1=TpHL (specify inputs that are causing the transition, i.e. which row. Also show if you picked max or typical Tp values)
Next… • XOR gates and Parity circuits • Comparators • Reading Wakerly CH-6.8-6.9