Catholic University, PUCRS (Brazil) Faculty of Informatics and Faculty of Engineering

1. Catholic University, PUCRS (Brazil) Faculty of Informatics and Faculty of Engineering Embedded Systems Research Group <http://www.inf.pucrs.br/gse> “PUC#SAT – Embedded Systems for Space Applications” by Eduardo Augusto Bezerra Faculdade de Informática, PUCRS October 2009

2. Introduction: motivation, objectives and contributions The Space Science Centre, INPE, GAPH and GSE FPGA based design for space applications The hardware description language issue HDL-based design: migrating from microprocessors to FPGAs The prototyping platform Case studies Dependability improvement Design methodology and strategy Implementation details Conclusions and on-going work Summary

3. Introduction: motivation, objectives and contributions The Space Science Centre, INPE, GAPH and GSE FPGA based design for space applications The hardware description language issue HDL-based design: migrating from microprocessors to FPGAs The prototyping platform Case studies Dependability improvement Design methodology and strategy Implementation details Conclusions and on-going work Summary

4. Motivation, Objectives and Contributions • Motivation: • Flexibility of developing HW in a similar way as SW (bug fixes, system upgrades), with no HW changes; • Flexibility to define as many independent memory modules (distributed memory) as needed, reducing the von Neumann bus bottleneck; • Microprocessors: applications have to adapt to the available architecture. FPGAs: architecture adapts to the application; • High performance with low clock, less power consumption, reduced board size; • A demand from the Brazilian space program for a TC/TM CCSDS based system.

5. Motivation, Objectives and Contributions INPE 2020 2010 2015 2020 CBERS-5B CBERS-5A CBERS-3 CBERS-4 CBERS-6A CBERS-6B MAPSAR-2 GPM Lattes-1 Amazonia-1 Amazonia-3 MAPSAR Amazonia-2 Lattes-2

6. Motivation, Objectives and Contributions Perfil da indústria espacial brasileira

7. Motivation, Objectives and Contributions Plataforma multi-missão (PMM) - Um suporte comum para diferentes satélites científicos de observação da terra. 600 a 1200 km de altitude, 300 kg carga útil e 250 kg de sistemas, US$ 15 milhões

8. Motivation, Objectives and Contributions

9. Motivation, Objectives and Contributions

10. Motivation, Objectives and Contributions MAPSAR (carga útil SAR)“Synthetic Aperture Radar”

11. Motivation, Objectives and Contributions LATTES-1 - Satélite Científico para Pesquisa Geofísica • Variação de temperatura na Estratosfera e Mesosfera • Propagação de ondas gravitacionais interplanetárias • Bolhas e irregularidades no plasma ionosférico • Conteúdo de vapor d’água na Troposfera Apontamento geocêntrico

12. Motivation, Objectives and Contributions El Niños mais intensos?

13. Motivation, Objectives and Contributions

14. Motivation, Objectives and Contributions

15. Motivation, Objectives and Contributions • Objectives • Graduate and undergraduate students training; • Develop an FPGA based system, targeting an anti-fuse device; • Consolidate a research group at PUCRSin the space applications field, developing knowledge, skills, and expertise; • Provide support to the local industry in the space field; • Main objective: Design and implementation of a CCSDS TM and TC system in an FPGA.

16. Main Objective Design and implementation of an on-board CCSDS TC/TM system in an FPGA. Spacecraft Telecommand Telemetry Target: receive telecommand and send telemetry (CCSDS) Ground Station

17. Motivation, Objectives and Contributions • Contributions: • Skillful people trained for R&D projects in the fields of configurable computing and on-board processing systems for space applications; • Definition of a strategy to implement RS/BCH software based algorithms in hardware (VHDL); • Efficient hardware implementation of RS and BCH algorithms; • IP cores for CCSDS stack implementation; • A basic CCSDS TM/TC system running on an FPGA (SRAM and anti-fuse) to be used in future INPE space missions; • Dependable FPGA applications for space systems.

18. Introduction: motivation, objectives and contributions The Space Science Centre, INPE, GAPH and GSE FPGA based design for space applications The hardware description language issue HDL-based design: migrating from microprocessors to FPGAs The prototyping platform Case studies Dependability improvement Design methodology and strategy Implementation details Conclusions and on-going work Summary

19. Supporting Team: The GSE Group Research Emphasis: Embedded Systems Application Area Emphasis: Embedded HW & SW for dedicate computing systems. http://www.inf.pucrs.br/gse Space Systems Mobility and Pervasive Computing Precision Farming (GPS/INS) Embedded RTOS RFID

20. Supporting Team: The Space Science Centre Professor Paul Gough,Department of Informatics,School of Science and Technology,University of Sussex,Falmer, Brighton. U.K.BN1 9QTTel: (44) (0) 1273 678421Fax: (44) (0) 1273 678399Email: m.p.gough@sussex.ac.uk Group Email: space@sussex.ac.uk

21. Modular Reconfiguration Parameterisable IP Construction Supporting Team: The GAPH Group Research Emphasis: SoC Modelling, design and validation at systemic levels Application Area Emphasis: Telecom Systems http://www.inf.pucrs.br/gaph IP Construction Reconfigurable Hardware Construction Modular Systems Construction Hardware Virtualisation IP cores Reconfigurable Systems

22. Supporting Team: Collaborators Faculty of Engineering, PUCRS Systems, Computing and Communications Group http://www.ee.pucrs.br/~sisc IPCT, PUCRS Microgravity Laboratory http://www.ipct.pucrs.br/~microg Innalogics Sistemas Computacionais Ltda. http://www.innalogics.com.br

23. Introduction: motivation, objectives and contributions The Space Science Centre, INPE, GAPH and GSE FPGA based design for space applications The hardware description language issue HDL-based design: migrating from microprocessors to FPGAs The prototyping platform Case studies Dependability improvement Design methodology and strategy Implementation details Conclusions and on-going work Summary

24. Design Decisions: The Description Language Issue • The first activity in a project should be to identify the problem’s complexity. • In complex (and large) projects, the solution will certainly involve some sort of systemic approach. • In mid-size projects a behavioural HDL solution may be sufficient. • In small projects a schematic entry or structural HDL solution may be a better option, but just in cases where designers have a hardware background.

25. Design Decisions: The Description Language Issue Modelling/System Description ( SystemC , SDL, CSP, Java, ...) Validation (Co - Simulation, Formal Verification) HW/SW Partitioning HW (HDL, occam) SW (C, occam) Co - Synthesis Synthesis Compilation Prototyping Software components Hardware (Library) components FPGA FPGA FPGA µ P (IP cores) FPGA analogic memory memory SoC

26. Design Decisions: The Description Language Issue public static int resultALU(int a, int b, int opcode, int mode, int cin) { a &= 0xF; b &= 0xF; opcode &= 0xF; mode &= 0x1; cin &= 0x1; int result = 0; result &= 0xF; if (mode == 0) { switch (opcode) { case 0: result = a – 1 + cin; break; case 5: result = (a & b) + (a | (~b)) + cin;break; case 6 : result = a - b - 1 + cin;break; case 7 : result = (a | (~b)) + cin;break; case 8 : result = a + (a | b) + cin;break; case 9 : result = a + b + cin;break; case 10: result = (a & (~b)) + (a | b) + cin;break; case 12: result = a + a + a + cin;break; } } return result; }

27. Design Decisions: The Description Language Issue public static int resultALU(int aIn, int bIn, int opcodeIn, int modeIn, int cinIn) { int a = aIn & 0xF; int b = bIn & 0xF; int opcode = opcodeIn & 0xF; int mode = modeIn & 0x1; int cin = cinIn & 0x1;int result = 0; if (mode == 0) { int addIn1 = a & b; int addIn2 = a | b; int aOrNotB = a | (~b); int aAndNotB = a & (~b); switch (opcode) { case 0: //result = a - 1; addIn1 = a; addIn2 = -1; break; case 5: //result = (a & b) + (a | (~b)); addIn2 = aOrNotB; break; } result = addIn1 + addIn2; result += cin; } // infer a 4 bit positive output - bitwise AND (output is now a known 4-bit value) result &= 0xF; return result; }

28. Design Decisions: The Description Language Issue a + Java code optimized manually -1 MUX a a addIn1 b + result b aOrNotB MUX result + aAndNotB MUX -1 a addIn2 0 + -b opcode . . . opcode

29. Design Decisions: The Description Language Issue • The description language issue (and tools) is a polemic topic and an important subject in all recent editions of DAC. • VHDL/Verilog are too low level for complex designs. • New abstraction levels eases design and verification. • VHDL is a good option for the case study (mid to low size design): • Designer is familiar with VHDL • Developing tools available

30. Design Decisions: The Description Language Issue

31. Design Decisions: The Description Language Issue

32. Design Decisions: The Description Language Issue

33. HDL-Based Design: Migrating from Microprocessors to FPGAs • Contribution: a guide fornew (V)HDL developers with a software background • VHDL for synthesis vs. simulation • Common mistakes • Coding style (naming conventions) • Implementing software structures in hardware • A framework for the design automation

34. Designer selection for the microkernel generation (HDLSysInt GUI) HDL template file(s) (text format) FSM file(s) (text format) Test vectors and test bench (text format) HDL source file(s) (text format) HDL source file(s) (text format) HDL source file(s) (text format) HDL-Based Design: Migrating from Microprocessors to FPGAs HDLLib Repository of HDL source modules (text format) HDLGen Generates HDL templates (Java program) HDLSysInt Generates a configurable microkernel, and the whole HDL system. Links the user’s application to the microkernel (Java program) HDLTestGen Generates test vectors for on-line and off-line tests, and HDL modules for on-line test (Java program)

35. HDL-Based Design: Migrating from Microprocessors to FPGAs

36. The Prototyping Platform

37. The Prototyping Platform

38. The Prototyping Platform

39. The Prototyping Platform: Virtex 4 ML 403

40. Case Studies • ALU 74158: small size design (capture schematic entry, VHDL structural, VHDL behavioural, Handel-C, Java Forge). • SVAL-HDL: mid-size design (VHDL structural, VHDL behavioural) • SVAL - on-board instrumentation module flown on a NASA sounding rocket, launched from Svalbard (Spitzbergen, Norway), in December 1997. The instrument reached a peak altitude of about 200 miles, and returned to Earth on a parachute, in 1 hour of launch. • Particle correlator: mid-size design (VHDL behavioural, Java Forge, FSM)

41. Case Study: SVAL-HDL • ACF: statistical method used to measure the degree of association between values in a single series separated by some lag. Telemetry request (HF) . FIFO2 512x9 I/P1 FSM2 Microcontroller (HF) Telemetry output (HF) Parallel to serial . I/P2 FIFO1 512x9 FSM1 . Parallel to serial FIFO2 512x9 . Next energy step Last energy bits Telemetry output (LF) Microcontroller (LF) Parallel to serial FIFO1 512x9 Telemetry request (LF) Flash RAM (holds FPGA configuration) PIC microcontroller (reconfiguration manager) Telemetry Telecommands Application inputs (e.g. channel of pseudo-random electron detection pulses) Xilinx Virtex FPGA

42. Case Study: SVAL-HDL Sussex correlator board (SVAL) 2 directions x ( HF + 2 x ( LF frequency ranges x 2 processing algorithms ) ) Sensor 10 virtual instruments HF ACF HF ACF 0 - 8 MHz 0 - 8 MHz Electron detections (Buncher) (Buncher) parallel to Earth's magnetic field odd energy odd energy LF ACF LF ACF sweep sweep 0 - 10 KHz 0 - 10 KHz even energy even energy (1 bit ACF) (1 bit ACF) steps steps odd energy odd energy LF ACF LF ACF sweep sweep Energy 20 KeV 0 - 3.3 KHz 0 - 3.3 KHz down to eV odd energy odd energy Spectrometer Electron (1 bit ACF) (1 bit ACF) steps steps even energy even energy LF ACF LF ACF sweep sweep 0 - 10 KHz 0 - 10 KHz even energy even energy (multibit ACF) (multibit ACF) steps steps 32 energy even energy even energy LF ACF LF ACF levels sweep sweep 0 - 3.3 KHz 0 - 3.3 KHz Electron detections odd energy odd energy (multibit ACF) (multibit ACF) perpendicular to steps steps Earth's magnetic field

43. Case Study: SVAL-HDL

44. Case Study: SVAL-HDL

45. Dependability Improvement Signature Analysis-Driven Refresh Without FPGA Replication

46. Dependability Improvement Masking Connectivity Faults

47. Introduction: motivation, objectives and contributions The Space Science Centre, INPE, GAPH and GSE FPGA based design for space applications The hardware description language issue HDL-based design: migrating from microprocessors to FPGAs The prototyping platform Case studies Dependability improvement Design methodology and strategy Implementation details Conclusions and on-going work Summary

48. Design Methodology and Strategy ACDH for themultimission platform (MMP)

49. Main Objective Design and implementation of an on-board CCSDS TC/TM system in an FPGA. Spacecraft Telecommand Telemetry Target: receive telecommand and send telemetry (CCSDS) Ground Station

50. CCSDS - Consultative Committee for Space Data Systems • Founded in 1982 by the major space agencies in the world. Multi-national forum for the discussion of common space communications issues; • Employed in a large number of scientific and commercial spacecraft; • Allows reduced costs for on-board, ground and test equipment, as well as for spacecraft testing in in-orbit operation.