Introduction to CMOS VLSI Design Sequential Circuits

1. Introduction toCMOS VLSIDesignSequential Circuits

2. Outline • Sequencing • Sequencing Element Design • Max and Min-Delay • Clock Skew • Time Borrowing • Two-Phase Clocking

3. Sequencing • Combinational logic • output depends on current inputs • Sequential logic • output depends on current and previous inputs • Requires separating previous, current, future • Called state or tokens • Ex: FSM, pipeline

4. Sequencing Cont. • If tokens moved through pipeline at constant speed, no sequencing elements would be necessary • Ex: fiber-optic cable • Light pulses (tokens) are sent down cable • Next pulse sent before first reaches end of cable • No need for hardware to separate pulses • But dispersion sets min time between pulses • This is called wave pipelining in circuits • In most circuits, dispersion is high • Delay fast tokens so they don’t catch slow ones.

5. Sequencing Overhead • Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. • Inevitably adds some delay to the slow tokens • Makes circuit slower than just the logic delay • Called sequencing overhead • Some people call this clocking overhead • But it applies to asynchronous circuits too • Inevitable side effect of maintaining sequence

6. Sequencing Elements • Latch: Level sensitive • a.k.a. transparent latch, D latch • Flip-flop: edge triggered • A.k.a. master-slave flip-flop, D flip-flop, D register • Timing Diagrams • Transparent • Opaque • Edge-trigger

7. Sequencing Elements • Latch: Level sensitive • a.k.a. transparent latch, D latch • Flip-flop: edge triggered • A.k.a. master-slave flip-flop, D flip-flop, D register • Timing Diagrams • Transparent • Opaque • Edge-trigger

8. Latch Design • Pass Transistor Latch • Pros + + • Cons

9. Latch Design • Pass Transistor Latch • Pros + Tiny + Low clock load • Cons • Vt drop • nonrestoring • backdriving • output noise sensitivity • dynamic • diffusion input Used in 1970’s

10. Latch Design • Transmission gate + -

11. Latch Design • Transmission gate + No Vt drop - Requires inverted clock

12. Latch Design • Inverting buffer + + + Fixes either

13. Latch Design • Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input • Inverted output

14. Latch Design • Tristate feedback +

15. Latch Design • Tristate feedback + Static • Backdriving risk • Static latches are now essential

16. Latch Design • Buffered input + +

17. Latch Design • Buffered input + Fixes diffusion input + Noninverting

18. Latch Design • Buffered output +

19. Latch Design • Buffered output + No backdriving • Widely used in standard cells + Very robust (most important) • Rather large • Rather slow (1.5 – 2 FO4 delays) • High clock loading

20. Latch Design • Datapath latch + -

21. Latch Design • Datapath latch + Smaller, faster - unbuffered input

22. Flip-Flop Design • Flip-flop is built as pair of back-to-back latches

23. Enable • Enable: ignore clock when en = 0 • Mux: increase latch D-Q delay • Clock Gating: increase en setup time, skew

24. Reset • Force output low when reset asserted • Synchronous vs. asynchronous

25. Set / Reset • Set forces output high when enabled • Flip-flop with asynchronous set and reset

26. Sequencing Methods • Flip-flops • 2-Phase Latches • Pulsed Latches

27. Review Timing Definitions

28. Timing Diagrams Contamination and Propagation Delays

29. Max-Delay: Flip-Flops 1. rising edge of clk trigger F1 2. data at Q1 after clk-to-Q delay tpcq 3. cont. logic delay to D2 4. setup time for F2 before rising edge of clk

30. Max-Delay: Flip-Flops tpd is the time allow for combinational logic design the CL block satisfying the constraint

31. Max Delay: 2-Phase Latches

32. Max Delay: 2-Phase Latches assume that tpdq1 = tpdq2 propagation delay D1 to Q1, D2 to Q2

33. Max Delay: Pulsed Latches tpdq : D to Q propa. delay tcdq : D to Q contamination delay tpcq : clk to Q propagation delay

34. Max Delay: Pulsed Latches If the pulse is wide enough, tpw > tsetup , max-delay constraint is similar to the two-phase latches except only one latch is in the critical path tpd < Tc - tpdq If pulse width is narrow than the setup time, data must set up before the pulse rises tpd < Tc + tpw – tpcq – tsetup

35. Min-Delay: Flip-Flops tcd minimum logic contamination delay If thold > tcd, the data can incorrectly propagate through F1 and F2 two successive flip flops on one clock edge, resulting in system failure

36. Min-Delay: Flip-Flops tcd minimum logic contamination delay of CL block 1. rising edge of clk trigger F1 2. after clk-to-Q cont. delay Q1 begins change 3. D2 begins to change after CL cont delay 4. D2 should not change for at least thold w.r.t. the rising clk, if D2 changes it corrupts F2 so

37. Min-Delay: 2-Phase Latches 1. Data pass through L1 from rising edge of 1 2. Data should not reach L2 until a hold time delay the previous falling edge of 2 i.e. L2 becomes safely opaque. We need tcd large enoughto have correct operation, meet thold requirement of L2

38. Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! Contamination delay constraint applies to each phase of logic for latch-based systems, but to the entire cycle of logic for flip-flops.

39. Min-Delay: Pulsed Latches Hold time increased by pulse width

40. Min-Delay: Pulsed Latches Hold time increased by pulse width tccq + tcd tpw + thold

41. Time Borrowing • In a flop-based system: • Data launches on one rising edge • Must setup before next rising edge • If it arrives late, system fails • If it arrives early, time is wasted • Flops have hard edges • In a latch-based system • Data can pass through latch while transparent • Long cycle of logic can borrow time into next • As long as each loop completes in one cycle

42. Time Borrowing Example

43. How Much Borrowing? 2-Phase Latches Pulsed Latches Data can depart the first latch on the rising edge of the clock and does not have to set up until the falling edge of the clock on the receiving latch

44. Clock Skew • We have assumed zero clock skew • Clocks really have uncertainty in arrival time • Decreases maximum propagation delay • Increases minimum contamination delay • Decreases time borrowing

45. Skew: Flip-Flops tpd: propagation delay of CL tpd tcd: contamination delay of CL tccq + tcd tskew + thold Launching flop receives its clock early, the receiving flop receives its clock late clock skew effectively increases the hold time

46. Skew: Latches 2-Phase Latches Latch-based design, clock skew does not degrade performance Data arrives at the latches while they are transparent even clocks are skewed. Latch based design systems are skew-tolerant.

47. Skew: Pulsed Latches Pulsed Latches If the pulse width is wide enough, the skew will not increase overhead If the pulse width is narrow, skew can degrade the performance

48. Two-Phase Clocking • If setup times are violated, reduce clock speed • If hold times are violated, chip fails at any speed • An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap times • Call these clocks f1, f2 (ph1, ph2)

49. Safe Flip-Flop In industry, use a better timing analyzer • Add buffers to slow signals if hold time is at risk Power PC 603 datapath used this flip-flop

50. Differential Flip-flops Accepts true and complementary inputs Produce true and complementary outputs Works well for low-swing inputs such as register file bitlines and low-swing busses When  is low, precharge X, X’ When  is high, either X or X’ is pulled down, cross-coupled pMOS work as a keeper Cross-coupled NAND gates work as a SR latch capturing and holding the data .