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Andreas Bompos Director Product Engineering

Electromagnetic Crosstalk Analysis and Sign-off For Advanced Node SoCs. Andreas Bompos Director Product Engineering. Electromagnetic (EM) Crosstalk. Unwanted interference caused by the E/M fields of one or more signals ( aggressors ) affecting another signal ( victim ). Electric Field Coupling.

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Andreas Bompos Director Product Engineering

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  1. Electromagnetic Crosstalk Analysis and Sign-off For Advanced Node SoCs Andreas BomposDirector Product Engineering

  2. Electromagnetic (EM) Crosstalk • Unwanted interference caused by the E/M fields of one or more signals (aggressors) affecting another signal (victim) Electric Field Coupling Magnetic Field Coupling Victim current induced by Aggressor current AggressorVictim ∝1/r ∝1/r2 Silicon Substrate Silicon Substrate

  3. Most Common EM Crosstalk Symptoms • Timing Problems • Logic Errors • Signal Shape Distortion and Increased Noise Level • Costly Mitigation Strategies

  4. Why ElectroMagnetic is Important? • Frequency escalation – upper 5G frequency bands! • Rapidly increasing data rates • Even higher integration and layout density (SoC) • Technology Scaling • FinFet uneven scaling • Small form factor packaging • Extensive use of Redistribution layers (RDL) • 3D Packaging • InFO, WoW, CoWoS, etc. • Near-threshold design

  5. Benefits of a Complete EM-aware Design Flow • Major reduction in: • Silicon SoC area • Power consumption • Significant improvement in: • Performance, quality • Data rates, speed • Significant reduction of: • Cost • TTM, TTV

  6. Helic products improve performance of SoCs by analyzing and eliminating EM Crosstalk risks Addressing EM Crosstalk in SoCs Helic engine provides full EM + silicon substrate modeling

  7. Distant loops with negligible coupling between them when standalone, couple strongly through the presence of a larger 3rd loop Catastrophic EM Crosstalk Hard to Discover in SoCs 30dB less isolation!

  8. ANSYS Pharos: Quantifying the EM Risks • Pharos analyzes the level of EM crosstalk between victim ports and aggressor nets • Helps select critical nets or areas that have to be carefully analyzed and simulated

  9. Pharos Value Proposition • Pharos helps uncover risks stemming from Electromagnetic crosstalk in high-speed and high-frequency SoC designs • Pharos identifies all potential electromagnetic “Aggressor” nets to user-defined “Victim” nets • It is an analysis tool at block level and a sign-off tool at chip-level

  10. From Analysis to Sign-off • At block level, Pharos accelerates post-layout simulation closure by assisting the smart selection of all the “EM critical” nets • The tool reports only those nets that should be extracted with full EM effects and avoids unnecessary time-consuming EM analyses and spice simulations • Post-layout extractions with EM/RLCk parasitics become smarter and spice simulations become very accurate and shorter

  11. From Analysis to Sign-off • As a sign-off tool at the chip-level, Pharos analyzes an SoC and reports all ”Aggressor” nets that couple strongly with sensitive parts of the design • These aggressor nets are marked by Pharos for re-design providing an EM-aware sign-off ECO • Pharos increases significantly the level of confidence at the sign-off step helping fully control risks associated with EM coupling or poor EM isolation

  12. Pharos Engine • Pharos under the hood consists of two main components: • A very high-capacity full EM extraction engine that generates an EM model of a design with thousands of nets and tens of thousands of ports • A massively parallel, frequency-domain spice solver that can simulate the AC response of a netlist with tens of billions of elements

  13. Features and Benefits

  14. Pharos Design Flow

  15. Pharos Reports • Pharos provides text–based reports that can be easily scripted to provide many different views of the analysis • “Risky” nets are reported for detailed EM extraction and circuit simulation

  16. PLL in SerDes Size: 0.22 sq.mm Number of nets/ports: 10/140 Process node: 16nm Metal layers analyzed: Top to top-6 Peak memory/runtime: 132GB/7h 40mins

  17. Pharos enables SoC designers • Quickly identify all potential aggressors per victim net on your SoC! • Focus on performing detailed EM analysis on the most critical victim/aggressor pairs • Perform circuit simulation at multiple frequency points of interest to identify EM crosstalk risks • ECO layout or circuit pre-tape out to avoid crosstalk issues based on accurate results

  18. END Thank you!

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