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Signal Processing Using Digital Technology

Signal Processing Using Digital Technology. Jeremy Barsten Jeremy Stockwell December 10, 2002 Advisors: Dr. Thomas Stewart Dr. Vinod Prasad. Digital Signal Processor. Project Description Preliminary Work Research Design Standards and Patents Goals Schedule. Project Description.

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Signal Processing Using Digital Technology

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  1. Signal Processing Using Digital Technology Jeremy Barsten Jeremy Stockwell December 10, 2002 Advisors: Dr. Thomas Stewart Dr. Vinod Prasad

  2. Digital Signal Processor • Project Description • Preliminary Work • Research • Design • Standards and Patents • Goals • Schedule

  3. Project Description • All purpose digital signal processor using FPGA/VHDL and ASIC/VLSI technology. • Useable for a variety of applications: • Audio and Video • Cellular Technology • Adapted depending on the application.

  4. Project Description • High-level Block Diagram: Input Processed Signal Signal DIGITAL SIGNAL PROCESSOR

  5. Filter Design • Manipulating a digital input utilizing multipliers and adders. • Direct Form II realization of an IIR Filter: X(n) w(n) b0 y(n) -a1 b1 -a2 b2 w(n-1) w(n-2) Z-1 Z-1

  6. Signal Converters • Each signal will be analog in nature. • Requires an analog-to-digital converter at the input stage and a digital-to-analog converter at the output stage. • Type of converter will be determined later.

  7. Adder and Multiplier • Any basic signal processor consists of different stages of addition and multiplication. • A n-bit by n-bit multiplication will take place and result in a 2*n-bit value. • This answer will be added to previous values stored in a data register (discussed later).

  8. Adder and Multiplier • Cellular Multiplication: a3 a2 a1 a0 b0 b1 b2 b3 p7 p6 p5 p4 p3 p2 p1 p0

  9. Adder and Multiplier • For 2’s compliment addition and multiplication: 2’s Complement Block Cellular Array 2’s B L O C K

  10. Adder and Multiplier x(n)-a1*w(n-1) -a1 -a2 w(n-1) w(n-2) x(n) x(n)-a1*w(n-1) Shows the consecutive steps in the addition, multiplication, and data management. Memory Management 16-Bit Multiplier 16-Bit Multiplier Memory Management 32-bit Adder/Subtractor 32-bit Adder/Subtractor

  11. Data Management • Need to store old calculated values for later use. • Need a “shift-and-store” type of data management. • Will deliver the correct data at the appropriate time.

  12. Data Management • The possibility of overflow exists in the addition and multiplication stage. • For this reason, a truncation circuit is needed to control and adjust the value of the adder/multiplier circuit. • Will also use truncation before sending out the final signal.

  13. Preliminary Work • Investigation of Xilinx compiler. • Ripple carry adder v. Carry look ahead adder. • Parallel multiplier v. Serial multiplier.

  14. Ripple Carry Adder * 16-bit ripple carry adder will have 34 gate delays

  15. CLA Adder * 16-bit CLA adder will have 10 gate delays

  16. Xilinx Implementation • Implemented both adders using VHDL. • Created simple adder in VHDL (a+b=c). • Compared results to see what type of adder was created by the compiler. • Results: • Checked results using FPGA board.

  17. Multiplier • Advantages and disadvantages of using a parallel multiplier v. a serial multiplier. • Investigate the feasibility of using a Parallel Multiplier. • Speed v. Area

  18. Signed Serial Multiplier • For a signed serial multiplier, it is necessary to sign extend. • For Example (-3 x 5): 1101(-3) x 0101(+5) 11111101 0000000 111101 + 00000 11110001(-15)

  19. Signed Serial Multiplier A B Sign Extension Shift Register Shift Register Adder/Subtractor Register Product

  20. Area v. Speed • Implemented Serial adder and simple AxB adder in VHDL.

  21. Area v. Delay (serial)

  22. Area v. Delay (parallel)

  23. Other Multiplier Options • It is possible to use a combination of parallel and serial multipliers. • For example it is possible to use two 8-bit parallel multipliers in series which will double the delay but will save space.

  24. Standards and Patents • Searched the Internet for standards and patents on digital signal processors. • Many of the standards were application specific. • Could not really find specific standards on digital signal processors.

  25. Hardware and Software Programs • Xilinx Foundation Software • Leonardo Spectrum • L-Edit Pro v8.2 • PSpice Circuit Simulation • Xilinx XC4005ePC84 FPGA Board • A/D and D/A converters

  26. Project Goals • Determine best trade-off between size and speed for the adder/multiplier circuit. • VLSI implementation of a 4-bit adder and multiplier. • Determine the number of bits used in our processor to ensure stability. • Complete data management and truncation block of the processor. • Decide on specific application.

  27. Project Schedule • January/February: • Complete adder/multiplier in VHDL and implement on the FPGA board. • Complete VLSI design of adder/multiplier circuit. • March: • Determine specific application and design the appropriate filter. • April: • Complete data management and truncation block. • Implement entire design on FPGA board and troubleshoot any errors that arise. • May: • Prepare final presentation and possibly present at Student Expo.

  28. Signal Processing Using Digital Technology Jeremy Barsten Jeremy Stockwell December 10, 2002 Advisors: Dr. Thomas Stewart Dr. Vinod Prasad

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