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Malleable Signal Processor: A General-purpose Module for Sensor Integration

Malleable Signal Processor: A General-purpose Module for Sensor Integration. Pat McGuirk Mission Research Corporation 5001 Indian School Rd NE Albuquerque, NM 87110-3946 (505) 768-7633 pmcguirk@mrcmicroe.com. Greg Donohoe Air Force Research Laboratory Kirtland AFB Albuquerque, NM

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Malleable Signal Processor: A General-purpose Module for Sensor Integration

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  1. Malleable Signal Processor: A General-purpose Module for Sensor Integration Pat McGuirk Mission Research Corporation 5001 Indian School Rd NE Albuquerque, NM 87110-3946 (505) 768-7633 pmcguirk@mrcmicroe.com Greg Donohoe Air Force Research Laboratory Kirtland AFB Albuquerque, NM (505) 846-4958 greg.donohoe@kirtland.af.mil Jim Lyke Air Force Research Laboratory Kirtland AFB Albuquerque, NM (505) 846-5812 james.lyke@kirtland.af.mil 2000 Military and Aerospace Applications of Programmable Devices and Technologies Conference Page 1

  2. Outline • Introduction / background • Theory of Reconfigurable Computing Appliances • Design of MSP • Application of MSP to Sensor Fusion Problems • Miniaturization strategy for MSP • Lessons Learned • Upgrade Track of MSP • Summary Page 2

  3. Introduction • This work addresses the problem of using reconfigurable processing in embedded, real-time systems • High performance, complex imaging sensors • High bandwidth interfaces (~gigabit/sec) • The Malleable Signal Processor (MSP) is an attempt to produce an appliance-like, modular approach to reconfigurable computer • Real-time operation • Reconfiguration / communication protocols • Multiple reconfigurable machines within an overall complex system • Multi-chip module (MCM) miniaturization Page 3

  4. Original problem MSP was intended to solve Sensor front end 1 ? Surveillance Detector ASP Dig. Readout Sensor front end 2 Detector ASP Dig. Readout ? Track to Malleable Signal Processor Readout = Detector readout integrated circuit (ROIC/Multiplexer) ASP = Analog signal processor and digitizer Dig. = Front-end digital pre- processing electronics Sensor front end N Detector ASP Dig. Readout • Original intent of MSP was to minimize need for custom hardware when multiple complex sensors are interchanged Page 4

  5. A contemporary view of MSP as a generalized approach for complex embedded systems Passive MSP #1 Fusion Processor Ladar MSP #2 Telemetry MSP #i item #n MSP #n analog digital MSP replaces custom digital content of custom sensors, reducing need to create custom processors in hardware Page 5

  6. Template of generic re-configurable processorEmbedded Version core * * * * * optional Page 6

  7. Top Level Diagram of MSP Sensor interface 2 Altera Flex 10K100A 4 banks 512Kx24 Asynch SRAM Sensor-tailorable, reconfigurable logic core for MSP sub-system 1 Altera Flex 10K100A, Myricom FI32 PHY Chip as low-level Myrinet interface Custom HW tailors interfaces to sensors or actuators High-speed (1 Gbit) interface for processed data transport Additonal sensor or actuator interfaces Local bus for clock and configuration management Non-volatile storage, like a “juke box” for multiple personalities. The “play list” can be controlled in a time sequence or by external events, such as a message or sensor ID code* Serial link to host or other MSP systems *ID triggering not implemented Page 7

  8. 200,000 gate field programmable gate array (FPGA) Self-contained memory banks Reprogrammable as required for new sensor algorithms To be implemented in both printed wiring board and multichip module forms MSP Core Page 8

  9. MSP management layer • Controls and interfaces MSP core to fusion processor • Personality control • Myrinet interface • Multiple MSPs can be linked to a common host Linking multiple MSPs to fusion fusion host MSP Network Page 9

  10. FPGA-Based Myrinet Interface Page 10

  11. PWRENB(3:0) ?? 80MHz OSC WEn SAN FI32 A(15:0) I/F HITACHI D(7:0) CONN. HN58V1001 EEPROM RES 128Kx8 n OEn A(16) 10K100A JTAG CONN. AIC51 XILINX/FLASH board SCLK0 SCLK0 SDOUT0 SDOUT0 P1(0) Am29LV800B Am29LV800B 1Mx8 MISC. I/O Am29LV800B DATA[[7:0] 1Mx8 FLASH 1Mx8 CONFIG,CS[2:0],WR & RD FLASH ATTN[2:0],DONE,STATUS FLASH 30MHz OSC DATA[[7:0] CONFIG,CS[2:0],WR & RD ATTN[2:0],DONE,STATUS Detailed Block Diagram of MSP Management Layer with Emphasis on Configuration Management Processor EOC ALOGEOC Bn ALOGBn CSn ALOGCSn PWEn MGMT LAYER BLOCK rev 4/16/99 CLK ALOGCLK PADDR(15:0) PRENn AIC BLOCK PWEn Ÿ ALOGPENB PDATA(7:0) CLKF(1:0) ALOGCLKF(1:0) MYR10K BLOCK Ÿ MISC. RESn RES. SIGNALS Xilinx/FLASH BLOCK Ÿ POEn CAPs to/from FI32 LCLK ?? Ÿ PBLOCK board LDO HCLK REG. HCLKENB ?? AIC51PENBn POWER MIC CONTROL PROMPENBn data 2954 ??? 3.3VSWITCHED clk HXTAL Rn OEn SERIAL r/o 11.0592 PROM WEn Wn CS1 ce/ HITACHI CSRAMn n HM62V8128 CS2 CSRAM RAM A(16) RBLOCK 128Kx8 ADDR(15:0) A(15:0) D(7:0) DATA(7:0) A30MHzC STRANS(3:0) ?? SRCV(3:0) ?? SDIN0 SDIN0 RDY_BSYN A0-A18 WRN was P1(1) P1(7) REN PROG Am29LV800B P2(0) DATA[[7:0] CSN 1Mx8 P2(1) OE# RSTn DQ0-DQ7 FLASH WE# PO(7:0) RY/BY# CE# Xilinx CE# CE# XC4005XL CE# A30MHzC A30MHzA JTAG A30MHzB LOCAL BUS JTAG BUS (TDI, TMS, TCK, TDO) A30MHzA A30MHzB Page 11 4/16/99 wlh

  12. MSP Application to Sensor Fusion • Multiple MSPs support a scale-able fusion paradigm • MSPs provide real-time bridges to a wafer scale fusion system • Sensor and fusion engine (SAFE) is a miniature interceptor super-computer • Two MSPs, 96 floating-point processors, with real-time synchronization and reconfiguration support • Easily adaptable to other needs Single MCM / interposer Brassboard 3D MCM stack KHILS live test DITP Sensor and Fusion Engine (SAFE) Page 12

  13. Ladar MSP and Focal Plane MSP configurations MSP core segment (common in all MSP designs) MSP management segment (common in all MSP designs) Mirror control (servo segment) (common in both MSP designs) Focal plane sensor adaptation segment (SAS) (2) Ladar SAS (customized for ladar, common to two receiver designs) Page 13

  14. FPA Application • FPA Operational Personality • Implement enough functionality into MSP Core so that the full FPA frame need not be sent to FP. • 100 Hz Frame Rate on 256X 256 FPA possible. • Incoming frames are ‘ping-ponged’ between two memory banks of one PLD. • Minimal latency in transmitting data over network • Target Identification • Reports pixels exceeding a given threshold and neighboring pixel values. • Target Tracking • For a given track gate, computes binary & intensity centroids • Noise Calculations • Computes background noise statistics on four corners of array. Page 14

  15. FPA Application (cont) • Sensor control • Generates all clocking signals for FPA. • ROI (Region of Interest) Server • Capability to send every nth frame to skip frames for lower bandwidth receive nodes (such as computer display). • NUC (Non-Uniformity Correction) on pixel by pixel basis • Time Keeping • MFA/MFI (Multi-Frame Averaging/Integration) • Servo control • Averaging of ADC converter values to improve noise. • FPA Calibration Personality • Generate Gain and Offset Coefficients on pixel by pixel basis. • Identify and flag pixels outside operational window • Monitor FPA temperature Page 15

  16. MSP Management for focal plane • Contains configuration management processor (CMP) and myri10k functions • CMP functions/interfaces (0.5W 5/3.3V) • core and myri10K configuration/re-configuration • gain and offset image semi-permanent storage • command interface to host (back connector) • test port access for bypass in test and debug • participate in timestamp distribution / sync • orchestrate function of other management layers • control clocking of core and myri10k • Myri10k functions (1.5W @ 3.3V) • operate Myrinet link (message routing, hand-shaking, flow control) Page 16

  17. Focal Plane SAS segments FPA SAS segment • Provides FPA sensor management and data extraction from RIRCOE 256x256 FPA • Custom design used in FPA MSP • 1st generation brassboards built and tested; 2nd available by Oct • Miniature versions available by March 2001 clock FIFO A/D to MSP core pixel data filter bias • Flight Cryostat Assembly SAS • Provides temperature control and monitoring of deware • Controls simulation sources • Custom design used in ladar MSP • Brassboard in design • Miniature version available by October 2000 to MSP core Page 17

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  19. Ladar Application • Operational Programmation • Descrambles, reorders, decodes, and buffers ladar frames for transmission over network. • Fast processing accomplished…data is fully processed on the fly and sent out when last ladar voxel received. • Reformats network ladar commands to JTAG signaling format for transmission to ladar. • Performs timekeeping functions • Servo Control Page 19

  20. EOO’s Ladar ‘Pizza Board’ Single Ended Signals LVDS Signal Pairs MSP TTL to LVDS TCK FAST STEERING MIRROR JTAG Lines For Ladar Command Interface TMS Front connector interface TDO Analog signals LVDS to TTL TDI SAFE system Servo \segment Ladar Clock Ladar Data Interface Lines Ladar Data[4..1] Digital signals x y x’’ y” x y To Line MSP SENSOR fusion Servo and ladar SAS segments Servo segment • Provides simple driver interface between MSP core and two-axis mirrors • Common design used in each of two MSP subsystems in SAFE • Brassboards built and tested • Miniature versions available by November 2000 • Ladar SAS segment • Provides simple digital low-voltage differential signaling (LVDS) driver between ladar receiver and MSP core • Custom design used in ladar MSP • Brassboard built and tested • Miniature version available by October 2000 Page 20

  21. Miniaturization Overview:Sensor And Fusion Engine (SAFE) • SAFE is a dense packaging of - • Sensor (Ladar and FCA/FPA) Interface Electronics • Analog and Digital Sensor Preprocessing • Steering Mirror Interface Electronics and Processing • Embedded Myrinet Crossbar • Scalable Fusion Processor • Configuration and Management Processors • Thermal Management System • Software & Firmware • Coordinated Program • AFRL/VS (SAFE/MSP) • AFRL/VS (Passive sensor) • AFRL/IF (Fusion) • AFRL/MN (KHILS testing) • SMDC (Ladar) • NRL (Test bed integration) Page 21

  22. MSP Brassboard MSP core Myrinet interface Page 22

  23. MCM Implementation of MSP Fabricated multi-chip module (many of the 1,225 I/O are not used) MSP Core floorplan Page 23

  24. Malleable Signal Processor Miniaturization Strategy 2x2 inch MCM FPA SAS 2x2 inch MCM FCA SAS 2x2 inch MCM SERVO SAS 2x2 inch MCM MSP Core 2x2 inch MCM MSP Mgt segment Sensor and Fusion Engine (SAFE) Page 24

  25. SAFE System* Ladar SAS WSSP Clock WSSP A,B,C XBAR Mgt C MSP B Mgt B MSP A 8 Mgt A #7 Power FCA SAS #6 FPA SAS #5 Servo B #4 Servo A ap #3 p #2 Micro-backplane Flap #1 *based on latest CHIWG Page 25

  26. Lessons Learned • Asynchronous SRAM hampers processing of FPA data • For conservative implementation, strobing of data requires 3 MSP clock cycles for write operation • Gate capacity limited • Started with 200,000 PLD gates and consumed most of the resources in FPA operational personality. • Approaching 90% logic cell usage on both PLDs in MSP Core • “If you build it, they will come” mentality towards PLD resources. Page 26

  27. Future Upgrades • Expansion of FPGA capacity in core and flash memory • Problem in obtaining bare die from Altera / Xilinx • New proprietary concept in exploration to permit continuous upgrades as new, more powerful FPGAs become available • Work with University of Tennessee on rapid-prototyping capability (DARPA Champion program) • KHOROS environment (graphically based programming) • Ability to exploit sensor-specific cueing to load personalities could permit high-performance plug-and-play concepts Page 27

  28. Summary • MSP developed for sensor interface applications • Established an initial concept of a reconfigurable appliance for use in complex systems • Real-time, miniature, embedded • Complex systems applications of MSP described • Each MSP dedicated to a different sensor • Each MSP networkable through “back-door” networks • Dedicated high-speed (1 gbit/sec) interface to fusion processor • Miniaturization strategy will result in 25:1 reduction in size and weight • Lessons learned and follow-on activities described Page 28

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