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Overview of CS 151

Overview of CS 151. Fall 2007. Combinational Logic Design. Simplifying a logic function using algebraic method Truth table and logic function representation for a given behavioral description of a design Design with gates, Mux, and decoder. Sequential Logic Design.

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Overview of CS 151

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  1. Overview of CS 151 Fall 2007

  2. Combinational Logic Design • Simplifying a logic function using algebraic method • Truth table and logic function representation for a given behavioral description of a design • Design with gates, Mux, and decoder

  3. Sequential Logic Design • Latches and flip-flops (timing diagram) • Finite state machine for a sequential design • Controller Design: • Finite state machine, • state table, • design of combinational logic of sequential circuit, • reverse of sequential design

  4. Data Path Component Design •  Register design, • Shift operation, multi-function register design • Adder/Subtractor design, • Shifter • ALU design • Counter/timer design • Comparator design • Register file

  5. RTL and High level design • RTL design • high level state machine • Data path design • Controller design (FSM, state table, logic) • High level state machine with memory components • Memory design : ROM, SRAM, DRAM, FLASH, Register File, Hierarchical memory design

  6. Combinational Logic Optimization • Two-level logic • K-map • Identify Prime implicants • Select min # of primes to covers the 1’s of the function • Multi-level • Trade-off between delay and area • Critical path delay

  7. Sequential Logic Optimization • State Minimization • implication table • State encoding techniques • Neighbor difference minimization • One-hot encoding • Output encoding • Mealy/ Moore Machines • FSM design, state table, Timing diagram

  8. Data path Component Optimization • Design of faster adders • Carry-lookahead adders • Generate and Propagate, Carry-look-ahead Logic • Hierarchical carry-look-ahead logic to generate larger adders • Select adder • Combined adders • Carry-ripple+CLA adders, etc. • Trade-off between area and critical path delay

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