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Adaptive Hardware Design for Digital Signal Processing

Explore FPGA's reconfigurability for DSP functions through a carry lookahead adder approach. Develop 8-bit and 16-bit DSP chips, memory cells, and registers. Reconfigure FPGA for real-time processing.

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Adaptive Hardware Design for Digital Signal Processing

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  1. Adaptive Hardware Design for Digital Signal Processing Advisor: Dr. Thomas L. Stewart By: Prabjot Kaur Alex Tan

  2. Presentation Outline • Project Goal • Project Description • Functional Description • Block Diagram • Changes • Main Problem • Solution • Design Approaches • Schedule

  3. Project Goal • Design a Digital Signal Processing (DSP) hardware device • Implemented With Field Programmable Gate Arrays (FPGAs). • Investigate the capability of FPGAs to perform different functions through reconfigurations of the hardware design.

  4. Project Description • Functional Description: • DSP is the process of manipulating a digital input. This process utilizes multipliers and adders to achieve this. • Typical Equation: • y(n) = a1*y(n-1)+a2*y(n-2)+......am*y(n-m)+b*x(n)

  5. x(n): 8 or 16 bit 2’s complement word Control Switch: Precision of the DSP function to be implemented y(n): The result of the DSP function. input x(n) output y(n) FPGA DSP Implementation Control Switch Project DescriptionFunctional Description contd.

  6. Changes • VHDL

  7. B3 A3 B2 A2 Bo Ao B1 A1 C3 C4 C1 Co C2 FA FA FA FA So S3 S2 S1 4-Bit Ripple Carry Adder Main Problem * n-bit ripple carry adder will have 2n+2 gate delay

  8. Solution • ALTERNATIVE: • Carry Lookahead Adder (CLA) • Required to build a Partial Full Adder (PFA) • Separates the parts of the full adder not involving the carry propagation path from those containing the path.

  9. S G P C PFA Block Xilinx Feature B A

  10. Carry Lookahead Adder (CLA)

  11. Comparison GATE DELAYS: CLA RCA 4-bit adder 6 gates 10 gates 16-bit adder 10 gates 34 gates 64-bit adder 14 gates 120 gates

  12. Design Approaches • Build and test an 8-bit adder • 16-bit adder and multiplier • Implementation into an FPGA • Build and test memory cells and registers • Complete an 8-bit and a 16-bit DSP chip • Reconfigure the FPGA between real time 8-bit and 16-bit DSP processing

  13. Schedule • Work Time: Jan. 24 - April 15, 2000 • Four main parts: • 2 weeks : Research and Learning • 3 weeks : Design and Building (more emphasis on Design) • 3 weeks : Design and Building (more emphasis on Building) • 3 weeks : Testing and recording Data • Time after April 15: Testing and getting ready for demo.

  14. Thank You! • Any Questions?

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