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S07: The BASYS 2 Board’s VGA Port

Learn about Cathode Ray Tube (CRT) displays, VGA controller design, RGB inputs, sync signals, and pixel clock for FPGA on the BASYS 2 board. Understand VGA interface creation for display screens.

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S07: The BASYS 2 Board’s VGA Port

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  1. Introduction to Digital Hardware Design S07: The BASYS 2 Board’s VGA Port By: Dr. Khaled Benkrid (Author) Revised by: Prof. W. Adi

  2. CRT Displays 1/2 • Cathode Ray Tube (CRT) displays use amplitude modulated moving electron beams to display input information on a phosphor-coated screen • Colour CRT displays use three analogue input signals: one for the red colour (R), one for green (G), and one for blue (B) • In addition, synchronisation (sync) input signals are used to control the refresh rates of the display

  3. CRT Displays 2/2 • Current waveforms that are passed through the CRT coils cause an electron beam whose intensity is dictated by the amplitude of the RGB inputs to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom • The brightness of display at any pixel on the display depends on the amplitude of the input signals RGB at that moment in time as the cathode ray moves over the surface of the display

  4. BASYS 2 VGA Port • The BASYS 2 board uses 10 FPGA output signals to create a VGA port with 8-bit colour inputs. 3 bits for Red 3 bits for Green 2 bits for Blue and two sync signals HS – Horizontal Sync. VS – Vertical Sync. • The colour signals use resistor-divider circuits to create eight signal levels on the red and green VGA signals, and four on blue (the human eye is less sensitive to blue levels) • A VGA controller must be designed on FPGA to drive the sync and colour output signals with the correct timing and display information

  5. VGA Controller 1/3 • The pixel clock defines the time available to display one pixel of information • The VS signal defines the refresh frequency of the whole display (practical frequencies lie between 50Hz and 120Hz) • The HS signal defines the horizontal retrace frequency • The number of HS pulses per VS pulse dictates the number of lines in the screen • These signals and their timings apply to both CRT and Liquid Crystal Display (LCD) Displays

  6. VGA Controller 2/3 • For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the following table gives the corresponding signal timings • Porch intervals are the pre- and post-sync pulse times during which information cannot be displayed

  7. VGA Controller 3/3 • A VGA controller circuit decodes the output of a horizontal-sync counter driven by the pixel clock to generate the HS sync signal. This counter can be used to locate any pixel location on a given row • A vertical-sync counter increments with each HS pulse can then be used to generate the VS sync signal. This counter can be used to locate any given row • These two continually running counters can be used to form an address into a video RAM which holds pixel values e.g. in RGB or any other pixel intensity format

  8. Lab Session 6 The sixth lab session (“ColouringTheWorld ” module) has two aims. Firstly it acts as an exercise to practice design for specification. Secondly it involves the creation of yet another standard module that will be used many times in the remaining labs including the final SNAKE application. The module in question is a VGA interface that allows for the control of individual pixel elements of a display screen (e.g. CRT or LCD)

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