III-V CMOS: Device Design & Process Flows

1. ESSDERC Workshop on Germanium and III-V MOS Technology , Sept. 19, 2008 III-V CMOS: Device Design & Process Flows M. RodwellUniversity of California, Santa Barbara SRC Nonclassical CMOS Research Center C. Palmstrøm, E. Arkun, P. SimmondsUniversity of Minnesota P. McIntyre, J. Harris, Stanford University M. V. Fischetti, C. SachsUniversity of Massachusetts Amherst M. Wistey, U. Singisetti, G. Burek, A. Gossard, S. Stemmer, R. Engel-Herbert, Y. Hwang, Y. Zheng, C. Van de WalleUniversity of California Santa Barbara P. Asbeck, Y. Taur, A. Kummel, B. Yu, D. Wang, Y. Yuan,University of California San Diego rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

2. Why Develop III-V MOSFETs ? If FETs cannot be further scaled, instead increase electron velocity: Id / Wg = qnsv Id / Qtransit = v / Lg InGaAs→ lower m*→ higher velocity ( need > 1000 cm2 /V-s mobility) Difficulties: High-K dielectrics III-V growth on Si building MOSFETs low m* constrains vertical scaling, reduces drive current

3. We Must Increase Drive Current To Reduce Delay Suppose we reduce Lg but keep Tox fixed ? Cgs is reduced, but Id /DV remains constant. Problem: Fixed Cparasitic ~er eo ; about 1 fF/mm. We have not reduced Cparasitic DV / Id Must increase drive current (per unit FET periphery) Instead, proportionally reduce both Lg and Tox : → Id / DV increases, Cgs remains constant → Cgs DV / Id & Cparasitic DV / Id are both reduced But drive current is limited by: source contact resistance and access resistance minimum gate dielectric thickness (tunneling) minimum channel thickness (Eigenstate Energy) low density of states in channel (Fin- & Multi-Channel FETs improve both gm / Gdsand Cgs / Cparasitic )

4. Low Effective Mass Impairs Scaling, Limits Current Low mass impairs vertical scaling: Well energy Approaches L-valley if well is thinner than 3-5 nm. → Hard to scale below 22 nm Lg . Low mass limits transconductance: where (n is the # of band minima) cdos comparable to 1 nm EOT oxide. Low mass limits charge, hence current Ef reaches EL at ~ 1013 / cm2 charge density ( 5 nm well)

5. Drive Current in the Ballistic & Degenerate Limits eot includes the electron wavefunction depth Inclusive of non-parabolic band effects, which increase cdos , InGaAs & InP have near-optimum mass for 0.4-1.0 nm EOT gate dielectrics

6. Device Design Target ( 22 nm Lg ) Device > 5 mA/mm at 700 mV overdrive 1013 /cm2 carrier concentration < 10 nA/mm when off Dielectric: EOT < 1 nm, 0.6 nm preferable Dit < 5*1011 / cm2 / eV Channel : <5 nm thick mobility > 1000 cm2/V-s at 5 nm thickness, 1013 /cm2 S/D access resistance: <10 Ohm-mm resistivity, >2*1013 /cm2 carrier density, < 5 nm thick

7. Gate Source Drain Design: MOSFET with Source / Drain Regrowth no gate barrier under S/D contacts high-K gate barrier Overlap between gateand N+ source/drain K Shinohara HEMTs: high S/D resistance, low gate barrier Implanted III-V MOSFETs:implants too deep, too lightly doped

8. Design: Densities, Resistivities, Thicknesses

9. Process Flow with MBE Source/Drain Regrowth Wistey et al 2008 MBE conference

10. Gate Stack: Multiple Layers & Selective Etches Wistey et al 2008 MBE conference Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric

11. Sidewalls must be narrow and low leakage Wistey et al 2008 MBE conference Problem: Thick sidewalls require large lateral recess, makes regrowth more difficult. Thin sidewalls can have high leakage current Electrostatics: Need sidewalls <5nm or recess doping >5x1018 /cm3 (Asbeck/Taur)

12. Recess Etch & Regrowth: Inter-Relationships recessed S/D raised S/D InGaAs/InP composite channel permits selective InGaAs wet-etch, stopping on InP regrowth initiated on InP (desirable ?) Raised S/D process: easier regrowth, needs thinner (5 nm) sidewall

13. Contact & Regrowth Interface Resistance Singisetti, Wistey

14. TEM of Regrowth: InGaAs on InGaAs Wistey et al 2008 MBE conference HRTEM InGaAs n+ regrowth Interface HAADF-STEM` InGaAs n+ Interface 2 nm

15. S/D Regrowth by Migration-Enhanced Epitaxy Wistey et al 2008 MBE conference MBE growth is line-of-sight → gaps in regrowth near gate edges MEE provides surface migration during regrowth→ eliminates gaps SEM Cross Section SEM Side View (Oblique) Top of gate SiO2 dummy gate SiO2 dummy gate Side of gate InGaAs Regrowth InGaAs Regrowth Original Interface SEM: Greg Burek SEM: Uttam Singisetti No gaps Smooth surfaces. High Si activation (4x1019 cm-3). Quasi-selective: no growth on sidewalls

16. Images of Completed Device Wistey et al 2008 MBE conference

17. Results & Status Singisetti et al, 2008 ISCS Extremely low drive current due to gaps between regrowth and gate SEM shows ~ 200nm gap on source & drain. Gap region is depleted of carriers because of surface states We will soon build new devices with M.E.E. S/D regrowth

18. Other Processes We Are Trying S/D MBE regrowth process is hard: developing a true 22 nm process on a 200 k$/year budget but to prove drive current capability we need a true 22 nm device Two other processes being developed (reduce risk): gate-last process→ S/D by MBE; regrowth not required other processes with ultra shallow N+ S/D regions

19. InGaAs/InP Channel MOSFETs for VLSI Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm Devices cannot scale much below 22 nm Lg→ limits IC density Little CV/I benefit in gate lengths below 22 nm Lg Need device structure with very low access resistance radical re-work of device structure & process flow Gate dielectrics, III-V growth on Si: also under intensive development

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21. Scaling: Constant Aspect Ratio for Constant gm/Gds Keep Lg / Tox constant as we reduce Lg

22. Rough Projections From Simple Ballistic Theory 22 nm gate length 0.5-1.0 fF/mm parasitic capacitances Channel EOT drive current intrinsic(700 mV overdrive) gate capacitance InGaAs 1 nm 6 mA/mm 0.2 fF/mm InGaAs 1/2 nm 8.5 mA/mm 0.25 fF/mm Si 1 nm 2.5-3.5 mA/mm 0.7 fF/mm Si 1/2 nm 5-7 mA/mm 1.4 fF/mm InGaAs has much less gate capacitance 1 nm EOT → InGaAs gives much more drive current 1/2 nm EOT → InGaAs & Si have similar drive current InGaAs channel→ no benefit for sub-22-nm gate lengths

23. We Must Increase Transconductance To Reduce Delay Suppose we reduce Lg but keep Tox fixed ? Cgs is reduced, but gm remains constant. Problem: Fixed Cparasitic ~er eo ; about 1 fF/mm. We have not reduced Cparasitic / gm Must increase transconductance Instead, proportionally reduce both Lg and Tox : → gm increases, Cgs remains constant → Cgs / gm & Cparasitic / gm are both reduced But Transconductance is limited by: source contact resistance and access resistance difficulties in reducing gate dielectric thickness difficulties in reducing channel thickness (Eigenstate Energy) low density of states in channel