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MSD System Design Review Agenda P11212 : LVE Controls, RF Module

MSD System Design Review Agenda P11212 : LVE Controls, RF Module. Meeting Purpose 1. Present an overview of the project. 2. Confirm understanding of Customer Needs and Engineering Specifications. 3. Review Concept Generation and Refinement process.

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MSD System Design Review Agenda P11212 : LVE Controls, RF Module

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  1. MSD System Design Review AgendaP11212 : LVE Controls, RF Module • Meeting Purpose • 1. Present an overview of the project. • 2. Confirm understanding of Customer Needs and Engineering Specifications. • 3. Review Concept Generation and Refinement process. • 4. Proposal for a design solution and analysis of benefits vs. disadvantages. • 5. Discuss Feasibility and possible alteration of plan. • Materials to be Reviewed • 1. Project Description • 2. Work Breakdown Structure • 3. Customer Needs • 4. Engineering Specifications • 5. Interface Document • 6. Concept SelectionMatrix • 7. Proposed Ideas • 8. LVE Controls vs. LV 1 Gen 1 Design and RP1 Gen 2 Design • 9. Project Plan Moving Forward • 10. Risk Management

  2. Meeting Timeline

  3. Work Break Down Structure

  4. Work Break Down Assignments • Wireless Interface – Dan • Microcontroller – Dan • Communication Bus – Gokhan • Logic Power – Nick • Motor Power – Nick • H-bridge Drivers – Gokhan • Pulse Width Modulation - Gokhan

  5. Customer Needs

  6. Engineering Specifications

  7. Interface Control Document

  8. Concept SelectionRF Module

  9. Concept SelectionMicrocontroller

  10. Concept SelectionMotor Control

  11. Concept SelectionMSA Communication

  12. System Analysis • Delay through transmission: • Theoretical message size: 18 bits • Single Message Latency: • Time through USART: 18b / 31kBps = 72us • Time through RF: 18b / 40kbps = 450us • Total time: 72us + 450us = 522us • Max messages: 5 • Max messages size: 54 bits • Max Message Latency: • Time through USART: 54b / 31kBps = 217us • Time through RF: 54b / 40kbps = 1.35ms • Total time: 217us + 1350us = 1.567ms • Forward Backward Left Right M1 + M1 - M2 + M2 - M3 + M3 - M4 + M4 - M5 + M5 - M6 + M6 - M7 + M7 - M8 + M8 – • 5 bit: instruction 0-31 • 4 bit: speed 0-15 • X bit: redundancy • 5 instructions at once • (5+4+9)*3= 54 bits/instruction set

  13. System Analysis • Heat Transfer Rate: • Q = ΔT/R • ΔT = Tinteral - Texternal • R = d/ka • d = material thickness • k = thermal conductivity • a = exposed surface area • so Q = ΔTka/d

  14. System Architecture

  15. Previous Architecture

  16. Previous Architecture

  17. Project Plan

  18. Project Plan Gannt Chart

  19. Risk Assessment

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