Department of Computer Science Saddleback College Shannon Alfaro

1. CS 3A: Introduction to Computer OrganizationExample MicroArchitectureTannenbaum 4.1.1, 4.1.2 Department of Computer Science Saddleback College Shannon Alfaro

2. MicroArchitecture Level • A brief look at our levels again… • We’ve looked at the lowest level : Digital Logic Level • Now we’ll look at the MicroArchitecture Level

3. Big picture

4. Design of MicroArchitecture • Depends on ISA being implemented • ISA: RISC: 1 instruction/cycle; SPARC CISC: 1 instruction/(>1cycle); Pentium • Want to: explain general principles of micro-architecture design but  THERE ARE NONE!! EACH IS UNIQUE

5. Example MicroArchitecture • Chosen a subset JVM for integer operations: IJVM : Integer Java Virtual Machine • Our microarchitecture will contain a microprogram (in ROM) whose job is to: • Fetch • Decode • Execute _________ instructions 1 blank

6. Example MicroArchitecture • Imagine the design of MicroArchitecture as the following code: • The microprogram has a set of variables • Values represent the ________ of the computer 1 blank

7. Example MicroArchitecture • IJVM Instructions: short; usually 1-2 fields • Every instruction has an ________ • Many instructions have _________ • Model of Execution: fetch-execute cycle 2 blanks

8. High Level Instructions The Language to be Implemented IJVM: ISA Instructions Compiler/ Assembler MicroProgram in CPU MicroInstructions

9. Memories….. • Remember When??? CPU = Controller + Datapath • Datapath: contains • ALU • Registers • inputs & outputs (not shown)

10. IJVM Datapath • Datapath: contains • 32-bit registers • registers are accessible only by micro-program at the microarchitecture level. • B-BUS: Contents of Registers • C-BUS: Output of ALU & can write to multiple registers at once • ALU

11. IJVM Datapath • Datapath: contains an ALU: • just like what we constructed in chapter 3 (remember our decoder + Adder/Subtractor & Logic gates?) • Needs 2 inputs: A(left) register H (1 source) B(right) Bus B (9 sources)

12. Stack Based Machine • Stack Based Machine: Operands are placed on a stack & result is stored on the stack • SP: top of stack pointer • LV: pointer to local variables

13. IJVM Instruction Set

14. Compiling Java to IJVM

15. IJVM Arithmetic Logic Unit • ALU Operation: • To load H: • choose an ALU function that • Passes the value at the B input through the ALU • Writes value back into H i.e. identity of B ALU Truth Table

16. IJVM Arithmetic Logic Unit • ALU Operation: • Read & Write in Same Cycle • Can happen with magic & timing 1st half of cycle you read register 2nd half you write ALU Truth Table

17. Datapath Timing • Propagation Delay • Just as in our homework problem, there is a delay before the output of our gates is stable • Δx before values is stable; then ALU & shifter can begin computation • Δy: ALU & Shifter outputs are stable • Δz: results propagated along C bus to registers • Rising Edge: Registers Latch values into memory cells • Falling Edge: • signals set up for output • Δw time passes before valid

18. Datapath Timing • Propagation Delay • Just as in our homework problem, there is a delay before the output of our gates is stable • Δy: ALU & Shifter outputs are stable • Δz: results propagated along C bus to registers • Rising Edge: Registers Latch values into memory cells • Δx before values is stable • then ALU & shifter can begin computation

19. Datapath Timing • Propagation Delay • Just as in our homework problem, there is a delay before the output of our gates is stable • Δz: results propagated along C bus to registers • Rising Edge: Registers Latch values into memory cells • Δy: ALU & Shifter outputs are stable

20. Datapath Timing • Propagation Delay • Just as in our homework problem, there is a delay before the output of our gates is stable • Δz: results propagated along C bus to registers • Rising Edge: Registers Latch values into memory cells • Δz: results propagated along C bus to registers

21. Datapath Timing • Propagation Delay • Just as in our homework problem, there is a delay before the output of our gates is stable • Rising Edge: Registers Latch values into memory cells

22. Datapath Timing • To Implement this requires: • Rigid timing • ______clock cycle • _________________ propagation delay • Fast load of registers from C Bus 2 blanks

23. Datapath Timing • Things to Note: • Falling Edge Signals Start of Bus Cycle • Rising Edge Signals End of Bus Cycle • ____ units are operating ____ the time. The values are garbage until the known delay has passed. • Clock Length >= Δw + Δx + Δy + Δz 2 blanks

24. Memory Operations • 2-ways to address memory: • 32-bit word-addressable memory • Memory Address Register (MAR) • Memory Data Register (MDR) • 8-bit byte-addressable memory port • Program Counter (PC) = MBR[7…0]; Read Only

25. Memory Operations • Register Combinations • MAR/MDR: used to read/write ISA-level data words • PC/MBR: used to read the executable ISA-level program(consists of a byte stream) • NOTE: MBR: additional open arrow • determines whether the MBR value placed on Bus is +ive or –ive

26. MicroInstructions • Recall… ALUs, Register, Buses • All have control signals • Actions determined by their truth table. • IJVM Datapath • 29 signals needed to control all of our components. • values of signals control which portions of the circuit are contributing to the final result of the bus cycle. These signals together create our Binary Micro-Instruction

27. MicroInstructions • Signals are divided up into 5 functional groups: • 9 signals to control writing data from the C bus into registers • 9 signals to control enabling registers onto the B bus for ALU input • 8 signals to control the ALU and shifter functions • 2 signals (not shown) to indicate memory read/write via MAR/MDR • 1 signal (not shown) to indicate memory fetch via PC/MBR

28. Memory Read Operation • 1st Bus Cycle: • Memory Address is loaded into MAR • 2nd Bus Cycle: • Data is fetched from Memory & stored in registers • 3rd Bus Cycle: • Data can now be used in an instruction

29. Memory Read Operation • NOTE: • We can start another instruction during the 2nd bus cycle • not one that needs this information from the previous read

30. MicroInstruction Format • 36-signals to 1 IJVM instruction • Groups: Addr: Contains the address of a potential next microinstruction JAM: Determines how next microinstruction is selected

31. MicroInstruction Format • Groups: JAM: Determines how next microinstruction is selected N: ALU result was negative A-B= -ive  A < B Z: ALU result was zero A-B = 0  A = B

32. MicroInstruction Format • Groups: ALU: controls the ALU & shifter functions C: Selects which registers are written from the C Bus Mem: Memory Functions B: Selects the B bus source

33. Finally…. • Here we are!!! Our Controller + Datapath!!! 

34. Sequencer • Responsible for stepping through the sequence of operations necessary for execution of a single ISA instruction. • Produce 2 kinds of information on each cycle • state of every control signal in the system • address of the microinstruction that is to be executed next

35. Control Store • Holds microprogram: can be implemented as memory (memory cells) or logic gates

36. Control Store • Accessed through MBR & MDR • Holds micro-instructions… NOT ISA instructions • Properties: • 512 words • 1 word = 36-bit micro-instruction • Has it’s own address register: MicroProgram Counter (MPC) • Has it’s own data register: MicroInstruction Register (MIR)

37. Important Difference…. • Main Memory: • Program Instructions; executed sequentially(except for branches) : a = a+b; a = a-b; a = a + b; • Control Memory: • Control words contain information on how to control datapath for the operation. • It is a Read Only Memory. • Next Instruction is part of instruction is in the Control Memory

38. Micro Program Responsibilities • The microprogram needs to: • __________________ • ______________________________________ 2 blanks

39. Simulation of Architecture