Introduction to Flash Memory

1. Introduction to Flash Memory 2006. 11. 15. Mobile Embedded System Lab. Kiseok, Choi

2. Table of Contents • Stateless PC • Flash Memory Basics • NAND vs. NOR • SLC vs. MLC • NAND Flash Memory • FTL (Flash Translation Layer) • An FTL Design Based on Log Blocks • The Log Block • The Map Block • SSD (Solid State Disk) • State-of-the-art Technologies • Research Issues • Summary

3. Stateless PC • Definition : The PC that has no states, especially non-volatile states.

4. Stateless PC Remove non-volatile states Current PC Stateless PC State • What’s in the portable storage? • Operating Systems • File Systems • Private data • Applications

5. Stateless PC • Storage for the states • Flash memory is a good solution for the physical storage. • Why flash memory? • Faster access • Shock / Temperature resistance • Smaller size • Lighter weight • Lower power • Noiseless (0dB)

6. Flash Memory Basics • Flash memory • A non-volatile semiconductor memory device • Key feature : • To overwrite data, the memory cell should be erased first. • Kinds of flash memory • NOR • Introduced by Intel in 1988 • Randomly access data, like a computer’s main memory • Use for executing program code • NAND • Introduced by Toshiba in 1989 • Smaller and denser. → NAND is better at storing data. • Faster erase and write time NOR NAND

7. NAND vs. NOR Pros of NAND Pros of NOR 1. Smaller cell size 2. Limited bad blocks allowed 3. Fast writing 4. Lower power consumption 1. Fast random (read) access We focus on the NAND flash memory! Cons of NAND Cons of NOR 1. Slow random (read) access 1. Larger cell size 2. No bad blocks are allowed 3. Slow writing 4. Higher power consumption For Code Storage For Mass Storage

8. NAND Flash Memory • Organization of NAND flash memory • Small-block flash memory • Each page is (512 + 16) bytes long • 32 pages in each block • Large-block flash memory • Each page is (2048 + 64) bytes long • 64 pages in each block • Page layout for small-block flash memory Block 0 Block 1 Block n-1 Page 0 512 16 Page 1 • Page layout for large-block flash memory 2048 64 Page m-1 chip Main Area Spare Area

9. NAND Flash Memory • Primitive operations of NAND flash memory • Read page • (chip #, block #, page #) • ~20 us • Write (program) page • (chip #, block #, page #) • ~200 us • Erase block • (chip #, block #) • ~2 ms

10. Flash Memory Flash Memory Flash Memory Flash Memory FTL (Flash Translation Layer) File System File System Read Sectors Write Sectors Read Sectors Write Sectors Mismatch! Read Sectors Write Sectors Read Write Erase FTL + Device Driver Device Driver + +

11. FTL (Flash Translation Layer) • Definition • Software layer that makes flash memory appear to the system like a disk drive • Challenges in FTL • Asymmetry in read and write speeds • No overwrite is allowed without erasing

12. FTL basics • Read request from upper layer • No problem. • Write request from upper layer • There is a problem. • Erase operation must be done first (the erase operation is performed in a block unit) to overwrite data.

13. An FTL Design Based on Log Blocks • Background • 2 kinds of blocks • Data block: block level managed block (most) • Log block: page level managed block (a few) • Temporary storage for small size writes to data blocks Data Block Log Block Write! Data is written to the log block valid valid valid valid

14. An FTL Design Based on Log Blocks • Whenever the log block is full, • We need to merge the data block and the log block.

15. An FTL Design Based on Log Blocks • Merge Operation • Log Block Merge Data Block Data Block Free Block Log Block valid valid valid valid valid valid valid valid Free blocks

16. An FTL Design Based on Log Blocks • Merge Operation (cont’d) • Log Block Switch Data Block Data Block Log Block valid valid valid valid valid valid valid valid Free blocks

17. An FTL Design Based on Log Blocks • Where is the mapping information? • Mapping information : logical address to physical address • It is stored in map blocks.

18. Map Block • The Map Block • Where to store the mapping information • Previous scheme: each page/block in the associated spare area in the form of logical address tags •  requiring scanning of the entire space of flash memory to collect logical address tags • Map blocks: dedicated blocks to enable faster startup and on-demand fetching •  using map blocks in a round robin manner • Map Directory: the map of the mapping table in SRAM and is used to locate each portion of the mapping table stored in map blocks •  the map directory is stored in a reserved area of the flash memory

19. SSD (Solid State Disk) • The disk that uses the semiconductor as storage • DRAM-based • Flash-based • P-ATA / S-ATA interface • FTL • NAND flash memory • Target markets • Enterprise server storage • Mainstream PC storage

20. SSD (Solid State Disk) • HYDRA project • 2005.9 ~ • Mtron + SNU • 3.5 inch engineering sample already released (PCMark 04)

21. State-of-the-art Technologies • In the perspective of the pure NAND • Copy-back operation • Using internal data copies, data transfer overhead can be removed (used for merge operations). • Cache programming • Besides the page register, there’s a cache register. • Using double buffering, throughput can be increased.

22. State-of-the-art Technologies • In the perspective of new-typed NAND • Hybrid systems are proposed. • Pure NAND is not well suitable for running applications • dynamic/static RAM component + NAND • OneNAND = SRAM + NAND • High performance (read/write) • More expensive and less energy efficient

23. Research Issues • How to handle of bad blocks • Initial bad block and run-time bad block • Usually handled by the “bad block table” method • Wear-Leveling • There’s a limit on the number of erases • About 100,000 times • Need to erase flash memory blocks evenly • How to improve performance effectively

24. Summary • Stateless PC will replace the current PC in the future. • Reliable & fast portable storage is required for non-volatile storage of states. • Flash memory is a good choice for storage. • So the research focused on how to improve flash memory performance/capacity/durability is required.