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Flash Memory 교육

Flash Memory 교육. FLASH BU Design Team Chung JunSeop. 2 Types of Flash memory. Program Store (NOR Architecture). Data Store (AND/NAND Architecture). Store program for a uP Store small amounts of data Fast random access Sector erase, byte/word program. Store large amounts of data

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Flash Memory 교육

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  1. Flash Memory 교육 FLASH BU Design TeamChung JunSeop

  2. 2 Types of Flash memory Program Store (NOR Architecture) Data Store (AND/NAND Architecture) • Store program for a uP • Store small amounts of data • Fast random access • Sector erase, byte/word program • Store large amounts of data • Slow random access • Fast serial access • Page erase and program • Lowest cost/bit • Some Typical Applications • Set-top box • Cellular phone • PC BIOS • DVD • Networking equipment • Some Typical Applications • Solid-state disk • Digital camera • MP3 player • Voice recorder • GPS navigation computer

  3. Flash Memory Application PC Bios Memory Card HDD Driver Data Flash Code flash Mobile Phone Data Flash Code Flash DVD Player Digital Camera Music Player Voice Recoder Modem PDA

  4. Flash suppliers’ Line Up Others    Mostly Data Flash manufacturers, but also some non-compatible Code Flash  Note: Not feature set compatible

  5. Memory Architecture FLASH BU Design TeamChung JunSeop

  6. 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Architecture - what is sector ? Sector - the minimum array unit for erase Usually, the size of sector is 64Kbytes/32Kword In the Flash memory, we can program data by the byte unit but erase data only by the sector unit - 64Kbytes. 4M X 8 memory array

  7. 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Architecture - the storage area Normal sector - Memory array for storing data Boot sector - Memory array for storing booting information Usually smaller than normal sector. Secsi sector - Memory array for storing security code or data which should not be changed. ★ the memory density = the normal sector size + boot sector size Normal sector 64 Kbytes Boot sector Secsi sector 64 Kbytes 64 Kbytes 64Kbytes 4M X 8 memory array

  8. Architecture - the memory array for replacement In the each sector, there is extra memory array called redundancy array. During testing in the manufacturer site, if the defect memory cell found, we replace defect one with redundancy memory array by the logic circuitry. Defect area Redundancy array Sector Sector This area behaves as a main cell instead of defect area 1 sector structure When defect area found

  9. Architecture - functional diagram of redundancy There is redundant memory array which is prepared for the failed memory cell. During the testing, cells which do not operates properly are replaced with the redundant memory array. Decoder Main Array Address Repair Block Diagram MainSA MainSA Red.SA Address Compare CBUSEN Output MUX CBUS RedS/A RedS/A Out Buffer Out Buffer Decoder Redundant Array Location : Bottom Right Pin Pin

  10. 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Architecture - the Top/Bottom boot sector According to the user’s system environment , starting address of boot sector can be 000xh(bottom type) or fffxh (top type) . Normal sector Add: 000xh Add: 000xh 64 Kbytes Boot sector 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Add: fffxh Add: fffxh Top type boot sector Bottom type boot sector

  11. 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Architecture - Dual Bank Some flash memory products (up to 32M flash) support dual bank operation The dual bank operation means that when we programming or erasing data in the one bank(ex: bank1), we can read data in the other bank(ex : bank2) Bank 2 Bank 2 Bank 1 Bank 1 Programming or erasing Reading the data ★ There is flash products which support more than 2 bank (called multi-bank)

  12. HY29BDS641 HY29BDS642 HY29BDS643 HY29BDS644 Bank1 0.5Mb 8Mb 16Mb 32Mb Bank2 63.5Mb 56Mb 48Mb 32Mb Architecture - Sliding Bank The bank size is not always fixed. It has many options and user can select the bank size on their system requirement. The table 1. shows the option of HY29BDS64x table 1. Sliding bank option table of HY29BDS64x ★ The sliding bank option can be easily implemented by the slight process change.

  13. Architecture - Dual Bank Configuration(Top type) BANK 2 Sliding BANK 1 SG Sector A<21:12> SG Sector A<21:12> SG Sector A<21:12> SG Sector A<21:12> 00 SA00 0000000 xxx SA32 0100000 xxx SA33 0100001 xxx SA34 0100010 xxx SA35 0100011 xxx SA36 0100100 xxx SA37 0100101 xxx SA38 0100110 xxx SA39 0100111 xxx SA64 1000000 xxx SA65 1000001 xxx SA66 1000010 xxx SA67 1000011 xxx SA68 1000100 xxx SA69 1000101 xxx SA70 1000110 xxx SA71 1000111 xxx SA96 1100000 xxx SA97 1100001 xxx SA98 1100010 xxx SA99 1100011 xxx SA100 1100100 xxx SA101 1100101 xxx SA102 1100110 xxx SA103 1100111 xxx 643 (16M) SA01 0000001 xxx SA02 0000010 xxx SA03 0000011 xxx SA04 0000100 xxx SA05 0000101 xxx SA06 0000110 xxx SA07 0000111 xxx SG05 SG09 SG13 SG01 SA08 0001000 xxx SA09 0001001 xxx SA10 0001010 xxx SA11 0001011 xxx SA12 0001100 xxx SA13 0001101 xxx SA14 0001110 xxx SA15 0001111 xxx SA40 0101000 xxx SA41 0101001 xxx SA42 0101010 xxx SA43 0101011 xxx SA44 0101100 xxx SA45 0101101 xxx SA46 0101110 xxx SA47 0101111 xxx SA72 1001000 xxx SA73 1001001 xxx SA74 1001010 xxx SA75 1001011 xxx SA76 1001100 xxx SA77 1001101 xxx SA78 1001110 xxx SA79 1001111 xxx SA104 1101000 xxx SA105 1101001 xxx SA106 1101010 xxx SA107 1101011 xxx SA108 1101100 xxx SA109 1101101 xxx SA110 1101110 xxx SA111 1101111 xxx SG01 SG06 SG10 SG14 SA16 0010000 xxx SA17 0010001 xxx SA18 0010010 xxx SA19 0010011 xxx SA20 0010100 xxx SA21 0010101 xxx SA22 0010110 xxx SA23 0010111 xxx SA48 0110000 xxx SA49 0110001 xxx SA50 0110010 xxx SA51 0110011 xxx SA52 0110100 xxx SA53 0110101 xxx SA54 0110110 xxx SA55 0110111 xxx SA80 1010000 xxx SA81 1010001 xxx SA82 1010010 xxx SA83 1010011 xxx SA84 1010100 xxx SA85 1010101 xxx SA86 1010110 xxx SA87 1010111 xxx SA112 1110000 xxx SA113 1110001 xxx SA114 1110010 xxx SA115 1110011 xxx SA116 1110100 xxx SA117 1110101 xxx SA118 1110110 xxx SA119 1110111 xxx 642 (8M) SG01 SG07 SG11 SG15 SA24 0011000 xxx SA25 0011001 xxx SA26 0011010 xxx SA27 0011011 xxx SA28 0011100 xxx SA29 0011101 xxx SA30 0011110 xxx SA31 0011111 xxx SA56 0111000 xxx SA57 0111001 xxx SA58 0111010 xxx SA59 0111011 xxx SA60 0111100 xxx SA61 0111101 xxx SA62 0111110 xxx SA63 0111111 xxx SA88 1011000 xxx SA89 1011001 xxx SA90 1011010 xxx SA91 1011011 xxx SA92 1011100 xxx SA93 1011101 xxx SA94 1011110 xxx SA95 1011111 xxx SA120 1111000 xxx SA121 1111001 xxx SA122 1111010 xxx SA123 1111011 xxx SA124 1111100 xxx SA125 1111101 xxx SA126 1111110 xxx SG16 SG01 SG08 SG12 17 18 19 20 21 22 23 24 SA127 1111111 000 SA128 1111111 001 SA129 1111111 010 SA130 1111111 011 SA131 1111111 100 SA132 1111111 101 SA133 1111111 110 SA134 1111111 111 Boot Wrapping Area SecSi Range (256Bytes) from to SecSi Range : 1111111 111 1111 1000 0000 : 1111111 111 1111 1111 1111 TOP : 80-FF BOT : 00-7F # 8

  14. Chip Architecture - HY29BDS64x XY PREDECODER A16 WAIT# REDUNDANCY CELL ARRAY A15 NC A14 BAA# A13 CFI & STATUS VCCQ Redundancy CTRL. Logic A12 CSM PSSM VSSP A11 SENSE AMPLIFIER & REFERENCE PART VSSSA A10 A9 YB MUX & DRIVER PART DQ15 A8 DQ7 A19 DQ14 A20 DQ6 VSSQ PAGE BUFFER VSSH ` DQ13 MEB IOMUX VSSSA DQ5 ADV# DQ12 ADDCTRL & ADDBUF CLK DQ4 XY PREDECODER HPATH WORD-LINE BOOTSTRAP VCCP VCCSA VCCH VCCSA VCCP WE# CLK BURST PATH RST# SENSE AMPLIFIER & REFERENCE PART LVCC DQ11 A21 YB MUX & DRIVER PART DQ3 BJT_REF CHIP_CTRL ACC DQ10 WP# DQ2 RBY# VCCQ A18 DQ9 A17 TRIM DQ1 A7 IOMUX DQ8 A6 PAGE BUFFER DQ0 A5 ` OE# A4 HPATH A3 VSSQ A2 NC A1 NC SECTOR A0 NC CE# XY PREDECODER

  15. General Features FLASH BU Design TeamChung JunSeop

  16. Flash Memory Product Naming Convention Synchronous Mode Read supported Super Low Power supported Flash Memory (F = 5V, LV = 3V, S = 2V) HY29(P,B)DS643T Top Boot Block supported( B: Bottom Boot) Made by Hynix Page Mode Read supported Density Bank size option Dual Bank Operation supported

  17. Features - General features(1) Manufacturer ID: 0xAD As of May, 2001 Product Features Temp Package Application Device ID Minimum Order Quantities Package Legend C - PLCC, T - TSOP G - PSOP, F - FBGA HY29F002 2M (x8), 5V Top Boot Only 45, 55, 70, 90ns C 32PLCC 32TSOP BIOS Top Boot - 0xB0 PLCC - 480 units TSOP - 780 units T&R - 1,000 units HY29F040A 4M (x8), 5V Uniform sector 55, 70, 90ns C 32PLCC 32TSOP Networking BIOS 0xA4 PLCC - 480 units TSOP - 780 units T&R - 1,000 units HY29F400 4M (x8/16), 5V Boot sector 55, 70, 90ns C 44PSOP 48TSOP CD-RW, HDD, Analog Modem Top Boot - 0x23 Bottom Boot - 0xAB PSOP - 510 units TSOP - 960 units T&R - 500/1000 units Current Product HY29F080 8M (x8), 5V Uniform sector 70, 90ns C 40TSOP Networking Game, STB 0xD5 TSOP - 960 units T&R - 1,000 units HY29F800 8M (x8/16), 5V Boot sector 55, 70, 90ns C 44PSOP 48TSOP DVD, STB Modem,Telecom Top Boot - 0xD6 Bottom Boot - 0x58 PSOP - 510 units TSOP - 960 units T&R - 500/1000 units HY29LV160 16M (x8/16) 3.0-3.6 (V),3.14-3.46 (W) 90, 120ns C 48TSOP STB, Networking Modem, PDA Top Boot - 0xC4 Bottom Boot - 0x49 TSOP - 960 units T&R - 1,000 units Full datasheets are available on www.us.hynix.com

  18. Features - General features (2) Product Key Feature Temp Package Application Device ID HY29LV160 Top Boot - 0xC4 Bottom Boot - 0x49 16M (x8/16) 3V(2.7-3.6)70, 90ns C/I 48TSOP 48FBGA STB, Wireless, Consumer HY29DL163* 16M (x8/16), 3V DB, 70, 90ns I 48TSOP 48FBGA STB, Wireless Top Boot - 0x28 Bottom Boot - 0x2B HY29DS163* 16M (x8/16), DB 2V(1.8-2.2),100,120ns I 48TSOP 48FBGA Mobile Top Boot - 0x6A Bottom Boot - 0x6E 2001 HY29DS323* 32M (x8/16), DB 2V(1.8-2.2), 100,120ns I 48TSOP 48FBGA Mobile Top Boot - 0x62 Bottom Boot - 0x66 HY29LV320 32M (x16) 3V(2.7-3.6), 70, 90ns C/I 48TSOP 48FBGA Server, Internet Modem, PDA Top Boot - 0x7E Bottom Boot - 0x7D HY29LV400 4M (x8/16), 3V 55, 70, 90ns C/I 48TSOP 44PSOP CD-RW,HDD Modem Top Boot - 0xB9 Bottom Boot - 0xBA HY29LV800 8M (x8/16), 3V 55, 70, 90ns C/I 48TSOP 44PSOP DVD, Modem Top Boot - 0xDA Bottom Boot - 0x5B HY29DL32X 32M (x8/16), 3V DB, 70, 90ns C/I 48TSOP 48FBGA STB, PDA Will be decided by June 2002 HY29LV640 64M (x16), uniform 80ns, versatile I/O C/I 48TSOP 48FBGA Networking, Flash Card 0x5F HY29LV650 64M (x8/16), 3V 80ns, Boot Sector C/I 48TSOP 48FBGA STB, Wireless 0x7F Top & Bottom use same ID HY29BDS64X HY29PDS64X Conti. Burst(22ns), 2V Dual(Page), 90ns, 2V I 56FBGA Mobile, STB TBA

  19. FBGA PLCC MCP TSOP VCC=2.0, 1.8V VCC=3.3V VCC=5V 8M, 16M, 32M, 64M 32M, 64M 2M, 4M PLCC, SOJ Features - Package type

  20. Features - The Pin configuration 22 16 A[21:0] : Address Pin DQ[15:0] : Data IN/Out Pin CE# : Chip Enable Pin OE# : Output Enable Pin WE# : Write Enable Pin RESET# : Reset Pin WP# : Write Protection Pin ACC : Acceleration Pin ADV# : Address Valid Pin CLK : Clock Pin BAA# : Burst Address Advance Pin WAIT : WAIT Pin A[21:0] DQ[15:0] CE# WP# OE# WE# ACC RESET# V CCQ HY29BDS64X ONLY ADV# CLK BAA# WAIT

  21. Read Operation FLASH BU Design TeamChung JunSeop

  22. Read - When we can read ? Vcc Power Up Read Mode Yes Special mode exit command If command issued RESET Pin = Low or LVCC If pass ? No Command Start & executing Reset Command

  23. Read Operation We have the three kinds of read operation in the hynix flash memory - Normal Read Operation - Page mode Read Operation - Synchronous Read Operation Single Synchronous mode Burst mode

  24. Read - Read time efficiency When we read 4 word/ 8 word data with the normal, page, burst read respectively, we can get total time as in the below table. Assumption : initial access time : 90nS page access time : 27.5nS burst access time : 22.5nS Asynchronous Synchronous Transfer Time Normal Page Burst 4 Words 90n * 4 = 360n 90n + 27.5n * 3 = 172.5n 22.5n * (4 + 3) = 157.5n 8 Words 90n * 8 = 720n (90n + 27.5n * 3) * 2 = 345n 22.5n * (4 + 3 + 4) = 247.5n As the more data we try to read, the difference among the each read mode gets bigger.

  25. Read - Internal operation flow Flash memory Address changed Set-up the B/L Output the data Data changed Set-up the W/L Sensing the data W/L : Word Line B/L : Bit Line

  26. Enb Ysel W/Ln Read - Sensing operation VCC VCC VCC VCC Dynamic regulator SAINR SAIN Sense Amp Enb Ysel Data out RW/L Main cell Reference cell

  27. Read - Simulation for normal read operation Add PAD AF<0> BA<0> ATDSUM YB_DRV PRECHB SALEAK WL SAOUT(E) SAOUT(P) SAOUTb(E) SAOUTb(p) OE_Enb IOPAD

  28. VTH = 0V RL VWL V3 VTH = 0V Cp2 CL V1 V2 Cp1 Kickb Kickb Kick Read - Boosting Circuitry V1 =V2 =Vcc, V2 =VWL = GNDt = 0 ..(1) When Kick node is precharged to Vcc V1 =Vcc +Vcc t = 0+ ..(2) When sw0 closed @ t =s V1 =V2 =2Vcc x (Cp1/(Cp1+(Cp2//CL)) t = s ..(3) V3 =V2 +Vcc t = s ..(4) After enough time when V3 =VWL VWL = V3 x (Cp2/(Cp2//CL)) VWL = {Vcc + 2Vcc x (Cp1/(Cp1+(Cp2//CL)) } x (Cp2/(Cp2//CL)) Let Cp2=4CL , Cp1 =4(Cp2//CL) , VWL =2.08Vcc The products using Vcc under 3.3V usually use boosting scheme to generate power for W/L. VWL 4.5 4.0 VWL Range 3.5 3.0 Vcc 1.8 2.0 2.2 1.6

  29. Read Operation - Normal Read The timing diagram for normal read t RC Addresses Addresses Stable t ACC CE# t OE OE# t t D OEH F WE# t t CE O H Outputs Output Valid RESET# RY/BY# 0 V

  30. Speed Option Test Setup Description -80 -90 -120 ns tRC Read Cycle Time Min 80 90 120 ns tACC Address to Output Delay CE# = Vil Max 80 90 120 ns OE# = Vil tCE Chip Enable to Output Delay Max 80 90 120 ns tOE Output enable to Output Delay Max 80 90 120 ns tOH Output Hold Time from Address, Min 0 ns CE# or OE#, Whichever Ocuurs First Read - The parameter used for normal read

  31. Read - What is the page reading ? In the normal read mode, we get output data after tACC (initial access time) from the address change, and if we want get other data , we also wait for tACC to get one. In the page read mode, once we wait for tACC, the data which can be got by changing A[1]. A[0] would be output only after tPAA which is shoter than tACC Address changes Address changes Address changes Address changes Normal Read tACC tACC tACC tACC Data out Data out Data out Data out Addresses except A[1], A[0] change Addresses except A[1], A[0] change Only A[0], A[1] changes Only A[0], A[1] changes Page Read tACC tPAA tPAA tACC tPAA tPAA tPAA tPAA Data out Data out

  32. Read - The internal operation of page read Memory array 16 16 16 16 Sense Amp X16 Sense Amp X16 Sense Amp X16 Sense Amp X16 16 16 16 16 A1 A1 A1b A1b Page buff X16 Page buff X16 Page buff X16 Page buff X16 A0 A0b A0 A0b 16 16 16 16 16 To data output

  33. Read Operation - Page Read The timing diagram for page read WE# ADR[21:2 ] ADR[1:0] CE# OE# DATA OUT t t ACC P ACC t CE t OE

  34. Read - What is the synchronous reading ? • 2 type of synchronous read mode • 1)SSR(Single Synchronous Read) • Data form memory array, and other Read data(ID,CFI) • 2)BR(Burst Read) • Data only from memory array • Synchronous mode의 setting 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle ADD DATA ADD DATA ADD DATA ADD DATA # of Cycle Synchronous Mode Enable 4 555 AA 2AA 55 555 C0 XXX See below Synchronous Mode Disable 4 555 AA 2AA 55 555 C0 XXX 00 • The information in the 4th cycle

  35. Read - The Single synchronous mode(SSR) - BAA Pin is always at High for read & write and there is no internal address increment by the CLP pin toggling CLK CLK BAA# BAA# t BACC ADV# LDA# ADR ADR t ACC2 CE# CE# OE# WE# DATA DATA OUT IN t ACC1 t DS t CE t DH t OE Single Read Cycle Write Cycle

  36. Read - The Pin used in the synchronous mode - The pins listed below are activated after synchronous command ‘setting 1. CLK Pin It defines frequency of synchronous more. In the synchronous mode, when ADV =Low CLK pin lathces start address internally, when BAA# = Low, rising edge of CLK increase internal address. 2. ADV# Pin ADV#= Low makes address on the address pin valid. 3. WAIT In the Synchronous Read, WAIT pin shows the validity of data on the data pins. When WAIT asserted, It means that data is not valid.

  37. CLK VALID ADR ADDRESS A ADV# CD = 2 DATA DATA DATA DATA BCIR = 1 A A+1 A+2 CD = 6 DATA DATA DATA DATA BCIR = 2 A A+1 A+2 Read - The CD(clock delay), BCIR CD In the synchronous read, there needs at least initial access time to get the first valid data. But the system only counts the number of clock, we need the number of clock worth initial access time. This number of clock is called CD - clock delay BCIR This parameter only applies to BR . It defines the internal address should be synchronized to 1 clock cycle or 2 clock cycle. It is set on the DQ7 when command setting. The ‘0’ means 1 clock cycle and ‘1’ means 2 clock cycle.

  38. Read - The example of calculating CD, BCIR Maximum CLK frequency in MHz for tACC, tBACC = CD 80/20 ns 90/22.5 ns 120/30 ns 33.3 29.6 22.2 50.0 44.4 33.3 66.6(BCIR=1) 59.2(BCIR=1) 44.4(BCIR=1) N/A N/A 55.5(BCIR=1) N/A N/A 66.6(BCIR=1) 2 3 4 5 6 N/A : Not Allowed 1) BCIR setting If the period of system clock is longer than tBACC , system cannot read in the burst mode with a clock cycle . In this case, system should use 2 clock as a cycle to read in the burst mode - BCIR =1. 2) CD calculation (tACC/tVACC = 90/22.5nS) i) fclk = 40 Mhz(period : 25 nS) CD * 25(nS) + 22.5(nS) > 90(nS) , the minimum CD is 3 ii)fclk = 60 Mhz(period : 16.9nS) As the period is longer than tBACC = 22.5nS, BCIR should be set to 1 CD * 16.9(nS) + 16.9 + 22.5 > 90(nS) , the minimum CD is 4

  39. Read - The internal operation of burst read Burst Read시 Data Flow Data Flow Xadd Memory Array Y-gate Yadd ADD CTRL S/A (16ea) S/A (16ea) S/A (16ea) S/A (16ea) Data를 출력하고 있음 S/A로 부터 Data를 받아들임 Page buffer Page buffer Data out

  40. Read Operation - Burst Read The timing diagram for burst read CLK VALID ADR ADDRESS A ADV# CD = 2 DATA DATA DATA DATA BCIR = 1 A A+1 A+2 CD = 3 DATA DATA DATA DATA BCIR = 1 A A+1 A+2 CD = 4 DATA DATA DATA DATA BCIR = 1 A A+1 A+2 CD = 5 DATA DATA DATA DATA BCIR = 1 A A+1 A+2 CD = 6 DATA DATA DATA DATA BCIR = 2 A A+1 A+2 WAIT #

  41. Read - The diagram for synchronous read

  42. Read - The continuous burst read • The continuous burst read • After the 1st address is latched, as the clock keeps toggling, the data also keeps outputting • with the address increment internally until the clock stops toggling and new address is latched. • During the continuous burst read, internally, the time when A5 changes and W/L changes, • there will be a latency. When the latency happens, the WAIT is asserted to inform the invalid • data of the system. 3. The option in the burst mode 3.1 WPOL : It defines the valid logic status of WAIT pin 3.2 WDEL : When WAIT pin changes it’s polarity , WDEL defines WAIT pin should synchronized with the current clock or one clock before Starting ADD (n ≤32) Dn D29 D30 D31 D32 D32 D32 D33 D34 Latency cycle (data is invalid) Starting ADD (33 ≤ n ≤ 64) Dn D61 D62 D63 D64 D64 D64 D65 D66 Latency cycle (data is invalid)

  43. A1,A0(of the starting address) latency time 0,0 0 clock(no latency) 0,1 1 clock 1,0 2 clocks 1,1 3 clocks About the Latency 1. When the latency occurs ? - If the starting address is not aligned as the first address of internal 4-word reading group, there will be a latency as belows 1)case1 - word line changes As the clock keeps toggling, internally we have a chance to change word line 2)cas2 - A5 changes(internally) Because of Y coding scheme, we could not read successive 4 word acrossing the YA at a time. 2. How many times latency occur during the continuous burst read ? If the increasing address meets the one out of 2 cases, the latency occurs. After the 1st latency, since the internal address is aligned in the right order by the circuit, we won’t have a latency any more - unless the host starts the new burst read. 3. How long the latency will last ? It’s upon the A1,A0 of the starting address.(refer to the table below)

  44. The burst sequence when the latency occurs. 1.Normal Continuos burst sequence CLK DQ Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 Dn+5 Dn+6 Dn+7 Dn+8 Internal address Reading An+1 ~ An+4 Reading An+5 ~ An+8 Reading An+9 ~ An+12 2.When the latency occurs- when w/l changes The below diagram is for 2 clock latency case where A1,A0 of starting address is 10. Latency clock CLK DQ D59 D60 D61 D62 D63 D64 D64 D64 D0 D1 D2 D3 Internal address Reading A63,A64 Reading A0 ~ A3(of next w/l) Reading A4 ~ A7(of next w/l) The w/l changes

  45. WAIT Pin Operation(1) The Polarity of WAIT Pin during initial access time CLK ADV CD=2 CD=2 WAIT BAA DQ Invalid data Invalid data D0 D1 D2 D0 D1 Initial access stage when BAA=Low Initial access stage when BAA=Toggling The WAIT goes low in the initial access time when ADV goes low or CEB goes low. If the BAA goes high , it doesn’t affect initial access latency time(CD) but it affects the data output, which means that the shape of WAIT is only decided by the CD not by the polarity of BAA. After initial access time passes, the 1st data comes out regardless of the polarity of BAA. If the BAA still remains high after initial access latency, the 1st data holds. After the BAA goes low, the data triggered by the rising edge of clock will change.

  46. WDEL & WPOL 1. WDEL( when WPOL= 0) C33 C34 C33 C34 C32 CL1 CL2 C32 CL1 CL2 CLK CLK ADV ADV latency = 2 clock latency = 2 clock WAIT WAIT DQ DQ D32 D31 D32 D32 D32 D33 D34 D31 D32 D32 D33 D34 Fig 2.WDEL=1 Fig 1. WDEL=0 1.1 WDEL = 0 The latency starts with the same clock which makes the latency. 1,2 WDEL = 1 The latency starts with the clock before one cycle which makes the latency 2. WPOL 1.1 WPOL = 0 : During the latency time, WAIT pin goes low 1.2 WPOL = 1 : During the latency time, WAIT pin goes high

  47. Command Operation FLASH BU Design TeamChung JunSeop

  48. The description about the command status • In the read mode, we can issue command. • Some command has a exit command. In this case , the exit command • returns device to read mode. • During the command executing , if vcc goes down under Vlko, the device • returns to read mode. • During the command executing , if RESET pin goes low, the device • returns to read mode. • If program/erase completed successfully, the device returns to read mode. • If program/erase completed failed , the device is stuck in a failed status, • so the system must issue reset command to return to read mode.

  49. Command cycle Program Command Sequence (last two cycles) Read Status Data (last two cycles) t t t A WC AS H Addresses 0x555 PA PA PA CE# t GHWL t OE# C H t WP WE# t t t CS WPH WHWH1 Data 0xA0 PD Status D OUT t DS t D H V CC t VCS

  50. Cycle 1st 2nd 3rd 4th Format Unlock1 Unlock2 command Address/Data Cycle 1st 2nd 3rd 4th 5th 6th Format Unlock1 Unlock2 command unclock1 unlock Address The format of command Most of the command has 4 cycle format. Sector Erase/ Chip Erase command have 6 cycle format. For this unlock, the code 555(add)/AA(data) ,or AAA(add)/55(data) is used.

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