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Extending Open Core Protocol to Support System-Level Cache Coherence

Extending Open Core Protocol to Support System-Level Cache Coherence. Konstantinos Aisopos Princeton Univ. Chien-Chun (Joe) Chou Sonics Inc. Li-Shiuan Peh Princeton Univ. core. core. IP. OCP Port. OCP Port. OCP Port. OCP Port. OCP Port.

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Extending Open Core Protocol to Support System-Level Cache Coherence

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  1. Extending Open Core Protocol to Support System-Level Cache Coherence Konstantinos Aisopos Princeton Univ. Chien-Chun (Joe) Chou Sonics Inc. Li-Shiuan Peh Princeton Univ.

  2. core core IP OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port Open Core Protocol (OCP) • What is Open Core Protocol (OCP)? A standard on-chip core interface specification. • Why do we use it? It decouples the cores from the NoC: ? ? ? Req Req Req Resp Resp Resp NoC ? ? Req Req Resp Resp memory I/O

  3. OCP: need to support cache coherence • Academic publications[1][2][3] point out the benefits of HW coherence. • Cache-coherent multi-core MPSoC products are released: • Freescale with PowerPC cores • PMC-Sierra • Cavium and Broadcom with MIPS64 cores • ARM with ARM MPCores • IP providers urgently pressing for OCP-IP to support HW coherence. [1] M. Loghi, M. Poncino, and L. Benini. Cache coherence tradeoffs in shared-memory MPSoCs. ACM Transactions on Embedded Computing Systems, 5(2):383 - 407, May 2006. [2] T. Suh, D. Kim, and H. S. Lee. Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. In Proc. DAC., pages 553 - 558, Jun 2005. [3] T. Suh, H.-H. S. Lee, and D. M. Blough. Integrating cache coherence protocols for heterogeneous multiprocessor systems, part 1. IEEE Micro, 24(4):33 - 41, Jul 2004.

  4. Benefits of hardware cache coherence • Enhanced performance vs. SW • Lower the time to market • Flexibility • Ease of programming

  5. Outline • OCP: Master-Slave Model • Upgrading OCP to support cache coherence • Formal Verification

  6. IP IP OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port OCP Port core Req Req Req Req Resp Resp Resp Resp Req Req OCP Port Resp Resp Req Req Resp Resp memory I/O OCP Port OCP: Master – Slave Model core Master Slave Req Resp NoC

  7. Clock Request l l t t e e s s n n e e n Write Data n u u a a q q t h h e e t r Accept Request r c r r c o o P P P r P e e C Response t v C e e l l s a O s s e e O a l n n n n S r o o n n M e e Read Data p p a a t v s s h h s e e a c c Accept Response r r a l S M Control Signals Test Signals OCP: Master – Slave Model • Unidirectional communication read, read-exclusive, write, broadcast

  8. Outline • OCP: Master-Slave Model • Upgrading OCP to support cache coherence • Formal Verification

  9. Upgrading Open Core Protocol(1) Encoding coherent requests • Requests in a non-coherent system: • READ • WRITE • Additional requests in a coherent system: • READ for ownership / shared • WRITE BACK ► Need more encodings for requests.

  10. Master A Master B l l t t e e s s n n e e n n u u invalidate or Modified  Shared a a q q read for ownership / shared Address X t h h e e t r r r r c c o o P P P r P e e C t C v e e l l s O e e s s a O a l n n n n r o o S n n M e e p p a a t v s s h h s e e a c c r r a l S M Upgrading Open Core Protocol(2) Receiving coherent requests • Typical invalidation coherence protocol: ► Status updates not in response to any request, thus cannot be supported by legacy OCP port. Clock Request Write Data Accept Request Response Read Data check sharing vectors… Directory Address X Sharers: Master B Accept Response Control Signals Test Signals

  11. l l l l t t t t e e e e s s s s n n n n e e e e n n n n u u u u a a a a q q q q h h h h e e e e r r r r c c c c r e e e e e e t v l l l l e e e e s s s s s a n n n n n n n n a l o o o o n n n n S M p p p p a a a a s s s s h h h h e e e e c c c c r r r r Upgrading Open Core Protocol(2) Receiving coherent requests : OCPi Request legacy / coherent Write Data Accept Request OCPce Port OCPce Port Response Read Data Accept Response Control / Test Request Accept Request Response OCPi Port OCPi Port Dirty Data Setup State Accept Response

  12. l l t t e e s s n n e e n n u u a a q q h h e e r r c c e e e e l l l l e e e e s s s s n n n n n n n n o o o o n n n n p p p p a a a a s s s s h h h h e e e e c c c c r r r r Upgrading Open Core ProtocolPutting everything together Coherence Enable Coherence State Request l l t t e e s s legacy / coherent n n e e n n u u a a q q h h e e c c r r Write Data Accept Request OCPce Port OCPce Port Response Read Data Setup State Accept Response Coherent Slave Coherent Master Control / Test Request Accept Request Response OCPi Port OCPi Port Dirty Data Setup State Accept Response

  13. Master A Master B Master C cache cache cache OCP wrapper OCP wrapper OCP wrapper M-hit Ocp : Ocp : Ip : Ip : Ip : Ip : Ip : Ip : Req Resp Resp Req Resp Req Resp Req self intervention system request intervention request a c r t k e n n a e a o d c m r w k _ g d e f l n d e a e o o a r e r d d t l a w _ a _ g w l h s d f e e o s h o d n _ & a m r r g k r _ o e c e e s f n a _ d m h t d a e a & r n e t e r d d OCP a t a Coherence NoC Ocp : Ocp : Ip : Ip : Req Resp Resp Req OCP wrapper Slave Memory and Directory Module Upgraded Open Core Protocol Example want to read & don’t have the copy S S M Main port Arrows : request / response Intervention port request / response

  14. Outline • OCP: Master-Slave Model • Upgrading OCP to support cache coherence • Formal Verification

  15. Formal Verification • Model checking tool: NuSMV (ITC-IRST & CMU) • Modeling: communicating components as FSMs and NoC as a black box. • Verification: by exploring the system’s entire state space. • Abstractions • Data: Boolean variable (up-to-date / stale). • A single memory address (non conflicting requests don’t cause races): single entry caches and memory. • 3 processor cores. (!) full exploration of state space takes about four days

  16. Formal Verification • Properties verified (in computational tree logic, CTL) • Correct responses/requests and transitive states • Mutual Exclusion • Staleness (up-to-date data) • Liveness (no deadlock, no livelock) • Schemes verified • MSI directory-based coherence scheme [Sonics Inc.] • MESI snoopy bus-based coherence scheme [MIPS Inc.]

  17. Conclusions • A core interface specification that supports coherence is expected to have strong impact on the MPSoC industry. • An backward-compatible coherent Open Core Protocol interface was introduced. • Standard schemes were formally verified to ensure protocol correctness.

  18. Acknowledgments • We would like to thank: • The OCP-IP Specification Working Group, David Lau, Yasuhiko Kurosawa, Jay Jayasimha, Drew Wingard, Wolf-Dietrich Weber, Steve Krueger, and Sanjay Vishin. • The Computer Architecture Reading Group in Princeton University, Carole-Jean Wu, Ilias Tagkopoulos, and Emmanouil Koukoumidis.

  19. Thank you THANK YOU! QUESTIONS?

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