Optimal-Complexity Optical Router

1. Optimal-Complexity Optical Router Hadas Kogan, Isaac Keslassy Technion (Israel)

2. Lookup Switching Buffering Router – schematic representation Router Problem - electronic routers do not scale to optical speeds: • Access to electronic memory is slow and power consuming. • Data conversions are power consuming as well. Opticto electronic Electronic to optic … … Optic to electronic Electronic to optic

3. Power consumption per chassis [Nick McKeown, Stanford]

4. How about an optical router? • No electronic memory bottleneck • No O/E/O conversions BUT: An optical router is thought to be too complex. Is it?

5. Objective: quantify the fundamental complexity of an optical router

6. Quantifying complexity • “Quantify the fundamental complexity of an optical router”  reduce into most basic building blocks • Switching – 2x2 switches(and input/output lines)

7. Basic optical buffering component • Buffering – 2x2 switches(and input/output/fiber delay lines) • Mode of operation: • (a) Write • (b) Circulate • (c) Read (a) (b) (c) 1 1 1

8. The complexity of a system is the minimal number of 2x2 switches needed to implement it.

9. 8 7 6 5 4 3 2 1 5 1 4 2 8 3 6 7 N 7 1 6 2 3 3 8 4 2 5 4 6 1 7 5 8 Quantifying complexity • Complexity lower-bound: To get a state-space of size K in time T, the minimal number C* of 2x2 switches needed is: • Examples: • NxN switch: • Time Slot Interchange with time frame N:

10. Quantifying complexity • A construction algorithm is said to be optimal if its number of 2x2 switches grows like the construction complexity. • Examples: • NxN switch (“Benes is optimal”): • Time Slot Interchange: [Benes ‘65] [Jordan et al. ‘94].

11. Optimal buffer emulation

12. 1 2 3 4 5 6 t Emulation definition • Original buffer: • Buffer emulation (with delay D): 1 2 3 4 5 6 t D

13. Emulation idea • Objectif: emulate buffer of size B • Universal buffer: any policy • Idea: schedule using frames of size B • During any frame of B slots, observe which packets leave the original buffer and color them in blue • After some pipeline delay, send these blue packets in the same order F - Frame of size B Frame-based scheduling Optical buffer

14. 6 3 2 6 1 1 4 1 3 5 5 3 2 3 4 6 6 1 Algorithm • Algorithm is optimal • Complexity Θ(ln B) • Complexity lower-bound Θ(ln B) (the Time Slot Interchange is a special case) departure 4 B 5 2

15. Optimal router emulation

16. Input 1 Output 1 … … Input N Output N What we want: an ideal router • An output-queued push-in-first-out (OQ-PIFO) switch. • OQ - Arriving packets are placed immediately in the queue of size B at their destination output. • PIFO – packets departure ordering is according to their priority.

17. What we want: an ideal router • Why it is ideal: • OQ: Work-conserving  best throughput and average delay. • PIFO: Enables FIFO, strict priority, WFQ… • But – up to N packets could be destined to the same output: • Speed-up for switch • Speed-up for queue • PIFO is hard to implement.

18. Finding the complexity • Direct calculation of complexity seems impossible – what are the states? • Alternative way of finding the complexity: • Find a lower bound • Find an upper bound via algorithm • Algorithm complexity = Θ (lower bound)  algorithm is optimal

19. Input 1 Output 1 … … Input N Output N Lower bound - intuition B Intuition: the complexity of an OQ-PIFO switch is at least Θ(N ln(N) + N • ln(B)) = Θ(N ln(NB)) At least Θ(Nln(N)) At least Θ(ln(B))

20. Lower bound • A frames switch (time/space switch): t=6 t=5 t=4 t=3 t=2 t=1 t=9 t=8 t=7 t=6 t=5 t=4 t=3 Frames switch 9 8 7 3 2 1 N 10 9 11 5 2 6 12 11 10 6 5 4 8 7 12 1 4 3 B • A frames switch is a special case of an OQ-PIFO switch. • The practical complexity of a frames switch: Complexity {OQ-PIFO} ≥ Θ(Nln(NB)) • Now, find an algorithm that reaches this lower-bound

21. X X Solving the speed-up problem Leaves output A at time 1 • Example: Emulating a non-idling OQ-FIFO switch: D1 Output A Input 1 A1 Output B … C1 … A2 Input N C2 … Using parallel buffers to resolve conflicts: • At most one packet can enter a buffer at each time slot (N-1 constraints). • A packet departing at time T should not enter a buffer with a packet departing at T (N-1 constraints).  2N-1 buffers are enough.

22. The pigeonhole principle • Proof intuition: Pigeons ↔ Packets Holes ↔ Buffers • For emulating PIFO behavior – • The departure process is slightly modified • 4N-2 parallel buffers are required Input 1 Output 1 … … … Input N Output N

23. An optical emulation of an OQ-PIFO switch The pigeonhole principle + Our emulation of an optical buffer = An optical OQ-PIFO switch Optical buffer Output 1 … … Output N Optical buffer

24. An optical emulation of an OQ-PIFO switch (4N-2)xN switch Nx(4N-2) switch Number of 2x2 switches = Θ(NlnN+NlnB) = Θ(Nln(NB)) = Θ(lower bound) algorithm is optimal B πB πB B B πB πB B ... B πB πB B

25. Conclusion • Buffer fundamental complexity = Θ(lnB) • OQ-PIFO router fundamental complexity = Θ(NlnNB) • Both can be reached using given algorithms

26. Thank you!