Problem - A3: Multi-Core STA

1. Problem - A3: Multi-Core STA 2011.03.18 Ching-Yi, Hsiu-Yi, Zheng-Shan, Jui-Hung

2. Path-sensitization Algorithm • Originating from Timed ATPG • Multi-core Timing Simulation • Additional Checking • Possible Arrival Time • Future Work

3. (X,[0,0]) (X,[0,0]) (X,[0,0]) Originating from Timed ATPG Target (0,[3,-]) To find an input vector that makes the side-input stable to 0 no earlier than t=3.

4. (0,[0,0]) (X,[0,0]) (X,[0,0]) Originating from Timed ATPG Target (0,[3,-]) (0,[1,1])

5. (0,[0,0]) (0,[0,0]) (X,[0,0]) Originating from Timed ATPG (1,[1,1]) Target (0,[3,-]) (0,[1,1])

6. (0,[0,0]) (0,[0,0]) (1,[0,0]) Originating from Timed ATPG (1,[1,1]) Target (0,[3,-]) (1,[2,2]) (0,[1,1]) (1,[1,1]) Value and time conflict!  backtrack

7. (0,[0,0]) (0,[0,0]) (0,[0,0]) Originating from Timed ATPG (1,[1,1]) Target (0,[3,-]) (0,[3,3]) (0,[1,1]) (0,[2,2]) That’s what we want.

8. Multi-core Timing Simulation • An array of values in each gate value[thread_id]  • An array of queues for event-driven simulation vector< queue<Gate*> > 

9. Additional Checking Tp 1 if ( Ts > Tp ) 2 Vs can be any value 3 Vp  controlling value 4 elseif ( Ts < Tp) 5 Vs  non-controlling value 6 Vp  can be any value 7 else ( min(Ts) <= Tp <= max(Ts) ) 8 If ( Vp is non-controlling value ) 9 select Vs non-controlling s.t.Ts <= Tp 10 else ( Vp is controlling value) 11 select Vs non-controlling 12 ||select Vs controlling s.t.Ts >= Tp Ts

10. Possible Arrival Time • In order to do those additional checkings, we must build up a list for each gate to keep up the possible arrival time. 1. A table using “bitset”  good for merging & already sorted 2. A list using “set”  good for searching & ensure uniqueness

11. Flow

12. Future Work • Finishing the remaining parts of path-sensitization. • Acceleration of the program.