ECE 511: Digital System & Microprocessor

1. ECE 511: Digital System & Microprocessor

2. Week Subject W1-W2 Digital Logic Review W2-W3 Microprocessor Architecture & Overview W3-W6 Microprocessor Instruction Set & Programming W6-W9 Memory Interfacing W10-W14 Parallel I/O Interfacing Course Outline

3. References • J. L. Antonakos, “The 68000 Microprocessor: Hardware and Software Principles & Applications,” 5th Ed., Pearson Prentice-Hall, 2004. • C. M. Gilmore, “Microprocessors: Principles & Applications,” 2nd Ed., McGraw-Hill, 1995. • A. Clements, “Microprocessor System Design,” PWS-Kent, 1992. • J. Palmer & D. Perlman, “Introduction to Digital Systems,” Schaum’s Outlines Series, McGraw-Hill, 1993.

4. Course Evaluation • Tests x 2 30% • Quizzes x 3 20% • Mini Projects 50%

5. If you have problems, please contact me: Ahmad Ihsan bin Mohd Yassin Rm. T2-A13-1A, Dept. of Comp. Eng. Faculty of Elect. Eng. UiTM, Shah Alam. 03-55436118, 017-2576295 *Please call before you see me.

6. Digital Logic Review: Part I ECE 511: Digital System & Microprocessor.

7. What we will learn in this session: • Review of logic gates. • Flip-flops. • Universal representation of logic gates. • Decoders.

8. Gates

9. What are gates? • Gates are: • Simple electronic devices. • Constructed using transistors. • Used to design digital systems. • Three basic gates: • AND • OR • NOT • Usually packed into ICs.

10. Gates as Building Blocks

11. A C AND B TRUTH TABLE A B C 0 0 0 1 0 0 0 0 1 1 1 1 Basic Gate - AND • The AND gate is similar to multiply operation.

12. A OR C B TRUTH TABLE A B C 0 0 0 1 1 0 1 0 1 1 1 1 Basic Gate - OR • The OR gate is similar to add operation.

13. TRUTH TABLE A B 0 1 NOT A B 1 0 Basic Gate - NOT • The NOT gate performs the inverse operation.

14. Extended Gates • Combination of basic gates to perform complex functions: • NAND • NOR • XOR • XNOR • Flip-Flops

15. TRUTH TABLE A B C 0 1 0 1 1 0 1 0 1 A 1 1 0 A C NAND C NOT AND B B NAND Gate • Adds NOT after AND gate. • AND outputs are inverted  NAND (NOT-AND).

16. A A C OR NOT C NOR B B TRUTH TABLE A B C 0 1 0 1 0 0 0 0 1 1 1 0 NOR Gate • Adds NOT after OR gate. • OR outputs are inverted  NOR (NOT-OR).

17. A XOR C B TRUTH TABLE A B C 0 0 0 1 1 0 1 0 1 1 1 0 XOR Gate • XOR performs the Exclusive Or operation. • When A=B, C=0; when A≠B, C=1.

18. A XOR B TRUTH TABLE A B C 0 1 0 1 0 0 A 0 0 1 C XOR NOT C B 1 1 1 XNOR Gate • Adds NOT after XOR gate. • XOR outputs inverted  XNOR (NOT XOR).

19. Flip-Flops

20. Flip-Flops • Extended gate. • 2 gates, feedback connections. • 2 inputs, 4 states. • Used as memory: • Each FF stores 1 bit. • Unchanged at “keep” state. • More complex ones may: • Use timing from CLK. • Perform bit toggle.

21. RS Flip-Flop • 4 states: • Three stable. • One not stable. • 2 inputs, 2 outputs. • May contain clock (CLK) signal.

22. RSFF - NOR Implementation S Q’ *Assuming initial condition: S = 0, R = 0, Q = 0 Q R Qprev S R Q Q’ N/A 0 0 0 1 Output unchanged 0 1 0 1 0 Output set (Q = 1) 1 0 1 0 1 Output reset (Q = 0) *As long as S=0 and R=0, Q will always remain at previous state. Doesn’t matter 1 1 N/A N/A Unstable

23. RS Flip-Flop (NAND Implementation) S Q *Assuming initial condition: S = 0, R = 0, Q = 0 R Qprev S R Q Q’ Q’ N/A 0 0 0 1 Output unchanged 0 1 0 1 0 Output set (Q = 1) 1 0 1 0 1 Output reset (Q = 0) *As long as S=0 and R=0, Q will always remain at Qprev. Doesn’t matter 1 1 N/A N/A Unstable

24. Clocked RS S Q’ CLK Q R Qprev S R CLK Q Q’ N/A 0 0 ↑ 0 1 Output unchanged Only active when CLK is ↑ 0 1 0 ↑ 1 0 Output set (Q = 1) 1 0 1 ↑ 0 1 Output reset (Q = 0) Reduced sensitivity to noise. Doesn’t matter 1 1 Doesn’t matter N/A N/A Unstable

25. Qprev S R Q Q’ N/A 0 0 0 1 Output unchanged 0 1 0 1 0 Output set (Q = 1) 1 0 1 0 1 Output reset (Q = 0) Q 1 1 Q Q Toggle JK Flip-Flop • Same as RS, but forbidden state used to toggle bit. • Can also be clocked using CLK.

26. Qprev S R Q Q’ N/A 0 0 0 1 Output unchanged 0 1 0 1 0 Output set (Q = 1) 1 0 1 0 1 Output reset (Q = 0) Q 1 1 Q Q Toggle JK Flip-Flop (Palmer & Perlman, pg. 200) J Q K Q

27. Clocked JK (Palmer & Perlman, pg. 200) J Q CLK K Q Qprev S R CLK Q N/A 0 0 ↑ 0 Output unchanged 0 1 0 ↑ 1 Output set (Q = 1) 1 0 1 ↑ 0 Output reset (Q = 0) Q 1 1 ↑ Q Toggle

28. D-Flip-Flop • Data latch. • Modification of RSFF. • Stores 1-bit of information. • Can be combined to store more. • How data stored in memory.

29. Qprev D EN Q Q’ Doesn’t Matter 1 1 1 0 Output set (Q = 1) Doesn’t Matter 0 1 0 1 Output reset (Q = 0) D-Flip-Flop D Q’ EN Q Only active when EN is 1

30. D-Flip-Flop: Timing Diagram D EN Q

31. Storing 8-bits using DFF D0 D1 D2 D3 D4 D5 D6 D7 DFF DFF DFF DFF DFF DFF DFF DFF EN Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

32. Asynchronous Latch • Allows both synchronous & asynchronous operations: • Synchronous: CLK driven (Clocked JK). • Asynchronous: similar to RSFF. • 5 inputs, 2 outputs: • J, K and CLK for synch. operation. • PR, CLR for asynch. operation.

33. PRE J Q CLK PRE K Q PRE CLR Q J Q 1 1 Follows J, K, CLK (Synch. JK) PRE CLR Q CLK 1 0 Q = 0, resets output. CLR 0 0 Follows J, K, CLK (Synch. JK) 0 1 Q = 1, sets output. K Q 0 1 Q = 0, resets output. 0 0 Not valid. 1 0 Q = 1, sets output. 1 1 Not valid. CLR Asynchronous Latch (Perlman, pg. 201)

34. Universal Gates – NAND and NOR

35. NAND and NOR as Universal Gates • In industry, NAND and NOR gates are most common. • Reason? • Can be used to represent any gate (functionally complete). • Easiest & cheapest to produce.

36. NAND Logic

37. NOR Logic

38. NAND Logic

39. NOR Logic

40. IC 4011 IC 7402

41. Decoders

42. Decoders • Electronic device that: • Reverse of an encoder. • “Translates” binary codes back into signal. • Converts n inputs into 2n combinations. • Uses: • Activate devices for use by µP. • Memory, I/O interfacing.

43. I0 I1 I2 I3 I4 I5 I6 I7 Y0 Y1 Y2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Encoder vs. Decoder 8  3 Encoder I0 I1 I2 Y2 I3 Y1 I4 Y0 I5 I6 I7

44. Encoder vs. Decoder 3  8 Decoder I0 I1 Y2 I2 Y1 I3 Y0 I4 I5 I6 I7 Y2 Y1 Y0 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

45. Y0 I0 = Y0Y1Y2 Y1 I1 = Y0Y1Y2 I2 = Y0Y1Y2 Y2 I3 = Y0Y1Y2 I4 = Y0Y1Y2 I5 = Y0Y1Y2 I6 = Y0Y1Y2 I7 = Y0Y1Y2 What Goes on Inside a Decoder?

46. Decoders in Action Code Device 000 LED 001 DC Motor 010 Memory #1 011 Memory #2 100 Memory #3 101 Memory #4 110 LCD Display Activate Signal Device Code Decoder

47. 74LS139 Dual 2-4 Line Decoder • Motorola 2-4 decoder. • 2 x decoders in one IC. • 16 pins total: • 2 inputs, 4 outputs (active low). • Vcc (±5V) and GND. • 2 x Enable pins.

48. O0a O0b Ea Eb O1a O1b A0a A0b O2a O2b A1a A1b O3a O3b 74LS139 Dual 2-4 Line Decoder

49. E I1 I0 O3 O2 O1 O0 1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 74LS139 Truth Table

50. 74LS138 3-8 Line Decoder • Motorola 3-8 decoder. • 1 x decoder in one IC. • 16 pins total: • 3 inputs, 8 outputs (active low). • Vcc (±5V) and GND. • 3 x Enable pins.