CML building blocks for high frequency addition in VLSI

1. CML building blocks for high frequency addition in VLSI Syed Irfan Ahmed Monday March 24th, TB202 Presentation for: High speed and Low Power VLSI design course Instructor: Dr. Maitham Shams

2. Introduction • CML stands for Current Mode Logic • Evolution : Derivative of the original Bipolar ECL • For CMOS, it is called MCML logic (or MOS CML) • We will take a look at the pros and cons of the CML logic • To justify the use of MCML for adders at high (RF) frequencies Our Aim Dept. of Electronics

3. High Speed Technologies • THREE MAJOR STYLES ECL, LVDS, CML • ECL (Pros) • ECL (1960) by Motorola, Variations (LVPECL, Pseudo ECL, Reduced Swing ECL (RSECL) • Differential or single ended • Well studied logic style for 30 years until 1990-onwards • ECL (Cons) • Power/negative VDD • Terminating Rail is required • Compatibility issues with other circuits mainly CMOS Dept. of Electronics

4. LVDS (Low Voltage Differential Signaling) • LVDS (Pros) • LVDS (1990) by National Semiconductors • Point-to-point transceiver applications • 1.25V  300 mV signal < 2 Gbps data rates • Designed to support a variety of computer buses • Low EMI and noise • No negative supply is required • Frequently used in Gbps short-range optical links • Used in Flat Panel Displays and notebooks • Ultra-low power consumption, Easy termination • LVDS (Cons) • Difficult to design and suited only for Tx/Rx apps • Cannot design cell libraries Dept. of Electronics

5. Why use CML ? • Differential topology to improve stability • Low voltage swing: (few hundred mV) • Improves delay performance • Reduces EMI and cross-talk • Reduces generated noise • Reduces power consumption • Can design MCML cell libraries • Constant current drawn from supply • CML (CONS) • Continuous static power dissipation • Logic depth up to a maximum of 3 for best results Dept. of Electronics

6. Principle of Operation • How does it work? (Musicer 2000) Dept. of Electronics

7. Performance of CML circuits CMOS CML Suitable for RF Dept. of Electronics

8. Full Adder Circuits Dept. of Electronics

9. Future directions • Compensation for Vth variations (Tanabe et al. 2001) Dept. of Electronics

10. DyCML (Dynamic CML) • Dynamic CML (Allam, Elmasry 2001) Advantages: • Elimination of static power • Faster evaluation period • Lower power and delay than MCML Dept. of Electronics

11. Self-timed CML • Self-timed CML (Anis, Elmasry 2002) Advantages: • Further elimination of unnecessary static power • Current source turns on only when required; No dissipation if the next data bit is similar to previous one • Uses a sense amplifier (similar to that used in memory circuits, with critical layout requirements. Dept. of Electronics

12. Conclusions • CML is a high-speed, low-power methodology for designing high frequency digital blocks • Timetable • Test Benches - First week of April • Simulations & Design - 17 - 24 April (check) • Adder Implementation - 22 - 23 April • Presentation - Week of 23rd April • Report Writing to be finished by 5th May • Simulations in 0.18u technology • Thank you for your attention Dept. of Electronics

13. References • Jason Musicer, M.Eng Thesis, UC. Berkeley 2000 • “Dynamic Current Mode Logic (DyCML), A New Low-Power High-Performance Logic Family”, Allam. W. M., Elmasry, M.I., IEEE 2000 CICC • “Dynamic Current Model Logic (DyCML): A New Low-Power High-Performance Logic Style”, Allam. W. M., Elmasry, M.I., IEEE, JSSC, Vol. 36, No. 3, March 2001 • “0.18um CMOS 10Gb/s Multiplexer/Demultiplexer Ics using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation”, Tanabe et al., IEEE JSSC, Vol. 36. No.6, June 2001 • “Self-Timed MOS Current Mode Logic for Digital Applications”, Anis M.H., Elmasry M.I., 2002 IEEE CNF paper Dept. of Electronics