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Synchronization (other solutions …). Announcements. Assignment 2 is graded Project 1 is due today. Critical Section Problem. Problem: Design a protocol for processes to cooperate, such that only one process is in its critical section How to make multiple instructions seem like one?. CS 1.
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Announcements • Assignment 2 is graded • Project 1 is due today
Critical Section Problem • Problem: Design a protocol for processes to cooperate, such that only one process is in its critical section • How to make multiple instructions seem like one? CS1 Process 1 Process 2 CS2 Time Processes progress with non-zero speed, no assumption on clock speed Used extensively in operating systems: Queues, shared variables, interrupt handlers, etc.
Solution Structure Shared vars: Initialization: Process: . . . . . . Entry Section Critical Section Exit Section Added to solve the CS problem
Solution Requirements • Mutual Exclusion • Only one process can be in the critical section at any time • Progress • Decision on who enters CS cannot be indefinitely postponed • No deadlock • Bounded Waiting • Bound on #times others can enter CS, while I am waiting • No livelock • Also efficient (no extra resources), fair, simple, …
Process 0 turn = 0; while(turn != 0); Critical Section turn = 1; Solution 1 (Two Processes) Shared: int turn; Initialize: turn = 0; Process 1 turn = 1; while(turn != 1); Critical Section turn = 0; Problem: Does not satisfy progress! Assumes strict alternation
Process 0 flag[0] = true; while(flag[1]); Critical Section flag[0] = false; Solution 1 (Two Processes) Shared: bool flag[2]; Initialize: flag[0] = false; flag[1] = false; Process 1 flag[1] = true; while(flag[0]); Critical Section flag[1] = false; Problem: Does not satisfy progress! Timing dependent What if you swap statement in the entry section?
Process i flag[i] = true; turn = j; while(flag[j] && turn == j); Critical Section flag[i] = false; Peterson’s Algorithm Shared: bool flag[2]; int turn; Initialize: flag[0] = false; flag[1] = false; turn = 0; Works for atomic load/stores! Special problem for multiprocessors
Solution 2: Disable Interrupts • Disable interrupts while process is in critical section • 2 approaches: • Scheduler checks if program counter is in critical section • Do not interrupt if it is • Pro: Fast Con: needs compiler support • Process disables interrupts before entering critical section • Enables on exit • Pro: Easy Con: when infinite loop in CS • Cons • Response time • Multiprocessors Critical section should be small! Process Disable interrupts Critical Section Enable interrupts Entry Section Exit Section
Solution 3: Hardware Primitives • Modern hardware provides better atomic instructions: • test_and_set • swap • compare_and_swap • load_linked/store_conditional • fetch_and_add • Entire function is atomic • Possible by locking bus for both load and store void swap(bool *a, bool *b) { bool temp = *a; *a = *b; *b = temp; } bool test_and_set(bool *target) { bool temp = *target; *target = TRUE; return temp; }
Process i While(test_and_set(&lock)); Critical Section lock = false; Solution 3: Hardware Primitives Share: int lock; Initialize: lock = false; Problem: Does not satisfy bounded waiting (see book for correct solution)
Hardware Primitives • Pros: • Simple primitive • Easy to program critical sections • Cons • Busy waiting for entire duration of critical section! • Also called spinlocks
Implementing Semaphores • P() and V() should be executed atomically • Disable interrupts, or • Busy waiting solutions • Move busy wait from entry of CS to P() and V() • P() and V() code is small
Semaphores Atomicity typedef struct semaphore { int lock; int value: ProcessList L; } Semaphore; void P(Semaphore *S) { while(test_and_set(&S->lock) == 1) /* do nothing */; S->value = S->value - 1; if (S.value < 0) { add this process to S.L; atomic_clear_and block(&S->lock); } else atomicclear(&S->lock); } void V(S) { while(test_and_set(&S->lock) == 1) /* do nothing */; S->value = S->value + 1; if (S->value <= 0) { remove a process P from S.L; wakeup P } atomicclear(&S->lock); }
A Real Race Condition • Customer to sales executive: “ This is the second time I have written to you, and I don't blame you for not answering me, because I sounded crazy, but it is a fact that as a tradition in our family we have ice-cream for dessert after dinner each night. …”