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SoCKET Workshop Introduction

SoCKET Workshop Introduction. Program (1st half day). 10h-10h30 Welcome and presentation of the SoCKET project (V.Lefftz, Astrium )  10h30-12h Description of the industrial case studies Avionics flight control remote module (P.Moreau, Airbus )

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SoCKET Workshop Introduction

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  1. SoCKET Workshop Introduction

  2. Program (1st half day) • 10h-10h30 Welcome and presentation of the SoCKET project (V.Lefftz, Astrium)  • 10h30-12h Description of the industrial case studies • Avionics flight control remote module (P.Moreau, Airbus) • Space high resolution image processing (V.Lefftz, Astrium) • Pedestrian tracking with smart cameras (P.Brelet, Thales R&T) • Controller for an absolute scalar magnetometer (J.Bertrand, A.Boness, CNES) • System for secure communication (P.Gouriou, Maya) Synthesis of critical embedded systems needs (V.Lefftz, Astrium) • Lunch

  3. Program (2nd hald day) • 13h30-14h20 Tutorial "SoC modeling with SystemC TLM" (L.Maillet-Contoz, STMicroelectronics) • 14h20-15h10 Tutorial "IP-XACT for critical system assembly and requirements traceability" (E.Vaumorin and R.Lucas, Magillem Design Services) • Break • 15h30-16h20 Tutorial "High-level synthesis" (P.Coussy, Lab-STICC UBS) • 16h20-17h10 Tutorial "Assertion-Based Verification (ABV): Verification of logical and temporal properties" (L.Pierre, TIMA Univ. Grenoble) • 17h10-18h Tutorial "Worst Case Execution Time: theory and practice" (H.Cassé, IRIT Univ. Toulouse)

  4. Program (3rd half day) • 8h–9h Presentation of the proposed design flow, and application to the different case studies (L.Maillet-Contoz, STMicroelectronics) • 9h - 10h45 SystemC modeling in the design flow • L.Letellier and P.Moreau (Airbus Operations S.A.S.) • A.Berjaoui, A.Lefèvre, C. Le Lann (Astrium) • A.Boness (CNES) • P.Brelet (Thales R&T) • Break • 11h15-12h IP-XACT in the design flow • L.Letellier and P.Moreau (Airbus Operations S.A.S.) • P.Brelet (Thales Research & Technology) • Lunch

  5. Program (4th half day) • 13h30-14h20 High-level synthesis in the design flow • J.Lachaize (Astrium) • P.Brelet (Thales Research & Technology) • 14h20-15h20 Verification in the design flow • L.Pierre (TIMA Univ. Grenoble) • V.Lefftz (Astrium), L.Pierre (TIMA Univ. Grenoble) • A.Boness (CNES) • 15h20-15h40 Debug in the design flow • P.Gouriou (Maya) • 15h40-16h20 Presentation of the demonstrations

  6. Demonstrations • 16h20-18h Break and demonstrations • High-Level Synthesis: an efficient solution to design hardware accelerators in SoC (Lab-STICC UBS) • FPGA implementation of the DSP unit and model of a magnetometric probe (CNES) • Automatic and efficient assertion-based verification for SystemC TLM hardware/software platforms (Airbus Operations S.A.S., Astrium, TIMA Univ. Grenoble) • Demonstration of object detection on a SoC (Thales Research & Technology)

  7. SoCKET Collaborative Project (SoC toolKit for critical Embedded sysTems) AEROSPACE VALLEY DAS Systèmes EmbarquésMINALOGIC Cluster EmSoC Vincent LEFFTZ - Astrium Satellites Mail: vincent.lefftz@astrium.eads.net

  8. SoCKET Administrative figures French poles of competitiveness project 5ieme FUI-AAP (5th Call to Project: Common Inter-ministries Funds) • Labelled by MINALOGIC(Grenoble) and AESE(Midi-Pyrenee) poles • Supported by ASTECH(Paris)/PEGASE(PACA)/AESE Alliance • Administrative Start: 2 June 2008 • Technical Start: 9 October 2008 • Official End: 30 November 2011 • 11 partners – 75 man.year - ~10M€

  9. Wording (1) • SoC = System On Chip • Integration on the same die of various HW IPs and SW parts providing a given set of functions. • SoC technology advantages: • Better performance • Better integration • Resources usage optimization • Mass and consumption gains • Reliability

  10. Wording (2) • Critical Embedded Systems: • Defined by safety level requirements • Safety level defined by the consequences of any deviation against the nominal behaviour putting in danger humans, goods, mission achievement, and/or economic returns • Require a certification agreed by internal or accredited third party audit

  11. Technological challenges • Application needs lead to develop more and more complex embedded systems at HW AND SW levels • Master this complexity is the key point for next industrial projects in order to improve the time cycle and the costs of critical embedded system development and its validation/qualification/certification • Define a “seamless” design flow built upon an integrated set of engineering tools to master this complexity and get the expected productivity gain

  12. Industrial challenges Aeronautics Certification of SoC-based systems -> time cycle, costs Distributed computers -> Miniaturization, wiring and mass Space data processing Qualification of SoC-based systems -> time cycle, costs Computing power -> new mission feasibility Complexity increase -> Integration without risk Electrical distributionCertification of secured power -> Secured application -> New markets Semiconductor industry High complexity SoCs with increasing volume of SW -> Time cycle, costs -> SoCs validation/certification -> New markets

  13. Context • Already established collaboration between aerospace industries (South-West of France) and semiconductor industry/academics (South-East of France) • Other projects address the SoC development problematic but not with the critical embedded system point of view

  14. Objectives • Define a “seamless” development flow, integrating the equipment qualification/certification, from the system level, to the IC and validated SW on these ICs; • Master the SoC solutions for critical embedded systems; • Master the “system dimension” (software + hardware) into the SoCs integration problematics; • Master the complexity, the time cycle reduction, design optimisation of SoC-based systems • Implement requirementstraceability through all the design flow; • Evaluate the HW simulation models (get from the design flow) usage for the integration and the validation of the critical embedded SWs.

  15. “Seamless” design flow

  16. “Seamless” design flow • Formalisms unification • Remove any semantic holes into HW/SW interfaces • Models transformation operators • Automation • Traceability • Overall coherency insurance • Tools interoperability • Keystone of 2 previous points

  17. TWINS Topcased OpenTLM HW/SW flow Tools &Methods Toolset for Virtual Prototyping Multival SoCKET Verification methods &performance analysis Tools & collaborativeplatform SystemC IPslibrary OPEES SoCLib XML Description IP-XACT Positioning vs other projects AADL->SystemCgenerator SPICES

  18. SoCKET: Consortium Security Camera Use Case IP-XACT • International groups: Airbus, Astrium, STMicroelectronics,Thalès R&T SystemC/TLM modelling Heterogeneous Simulation Techniques HLSGaut • PMEs: • PSI-S, PSI-E, Magillem Design Services ABVISIS & HORUS Secondary Flight Control Computer SoC Debug & Trace SW Secure Architecture • Academics and Research Centers: • CNES, IRIT, Lab-STICC, TIMA SW Properties WCETOTAWA Swarm MagnetometerComputer Image ProcessingMoving Object Tracking & Compression

  19. Thank you for your attention ? ? ? Any questions ?

  20. Conclusion • Presentation: Available Next Week http://socket.imag.fr • Semiconductor world and critical embedded systems industries cross-fertilization • 1st prototype enabling the maturation of the Critical Embedded Systems needs • Various projects started or are currently brewing to refine and complete the design flow Workshop - November 2011

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