'Digit serial multiplier' presentation slideshows

Reducing Energy in FPGA Multipliers Through Glitch Reduction

Reducing Energy in FPGA Multipliers Through Glitch Reduction. Nathan Rollins and Michael J. Wirthlin. Department of Electrical and Computer Engineering Brigham Young University Provo, UT. This work was supported by the NASA Earth-Sun System Technology Office as sub-contract with USC-ISI.

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