Reducing Energy in FPGA Multipliers Through Glitch Reduction

1. Reducing Energy in FPGA Multipliers Through Glitch Reduction Nathan Rollins and Michael J. Wirthlin Department of Electrical and Computer Engineering Brigham Young University Provo, UT This work was supported by the NASA Earth-Sun System Technology Office as sub-contract with USC-ISI

2. FPGAs’ High Power Consumption • Flexibility and reprogrammability result in greater power consumption relative to ASICs • Static power is insignificant compared to dynamic power consumption • Dynamic power consumption: Pavg = ½ ΣCn·fn·V2 n є nets

3. FPGAs’ High Power Consumption • fn term represents the net switching activity • Some net switching activity is unproductive: glitches • Large amount of dynamic switching power wasted in glitches • Goal: Lower energy by reducing the amount of glitching

4. FPGA Glitching Example • Glitching caused by unequal • logic and interconnect delays LUT 4 A OUT B C 0 D

5. FPGA Glitching Example • Glitching caused by unequal • logic and interconnect delays 1 LUT 4 A OUT B C 1 D

6. FPGA Glitching Example • Glitching caused by unequal • logic and interconnect delays 1 LUT 4 A Glitch OUT 1 B C 0 D

7. Glitch Glitch FPGA Glitching Example • Glitching caused by unequal • logic and interconnect delays 1 LUT 4 A OUT 1 B 1 C 1 D

8. Glitch Glitch FPGA Glitching Example • Glitching caused by unequal • logic and interconnect delays 1 LUT 4 A OUT 1 B 1 C 1 1 D

9. Power Classification • Design Static Power: divide the total static power of the device by the relative size of the circuit Total Static Power / (Circuit LUTs / Total LUTs) • Dynamic Glitching Power: % of signal glitches to total transitions is used to divide dynamic power into dynamic glitching and useful dynamic power • Useful Dynamic Power: the “useful” transitions of the circuit

10. Reduce Glitches with Pipelining • Pipelined designs have less logic and interconnect between registers • Pipelining causes long routes to be broken up • Pipelining in FPGAs can come at little additional cost

11. Pipelined Multiplier • Long carry chain paths of multiplier stages are ideal for pipelining • Pipelining gradually inserted in multipliers of different bit widths: • 4x4 • 8x8 • 16x16 • 32x32

12. 8-Bit 4-Bit 0.2% 0.2% 12.5% 46.6% Dynamic Glitch Power Static Power 87.3% 53.2% 16-Bit 32-Bit 0.1% 0.0% 68.2% 75.9% 31.7% 24.1% Multiplier Power Classification Useful Dynamic Power

13. Reduce Glitches with Pipelining • Pipelining reduces glitching and lowers power

14. Extreme Pipelining: Digit-Serial • In an FPGA an NxN array multiplier can have N pipeline stages • A digit-serial multiplier provides pipelining at a smaller granularity • Digit-serial operations can increase throughput – but also increase latency • Different digit sizes of digit-serial multiplier used: 1, 2, 4, 8, 16, 32

15. Pipelined vs. Digit-Serial Multiplier: Total Power Consumption • Digit-serial multiplier has almost no glitching - dynamic glitching power accounts for < 1% of total power Digit-serial Multipliers Array Multipliers

16. Operation Energy • Most studies focus on quantifying circuit design power only – often energy is a more useful metric • Four metrics can be used for energy consumption • Energy per Operation • Energy Delay • Energy Throughput • Energy Density

17. Pipelined vs. Digit-Serial Multiplier: Energy Per Operation • Quantifies the amount of energy required to complete a single operation (in nJ) Eop = P·tclk·n Digit-serial Multipliers Array Multipliers

18. Pipelined vs. Digit-Serial Multiplier: Energy Delay • Combines the energy efficiency and speed of an operator into a single parameter (in nJ ns) Edelay = P·tclk·tmin·n Digit-serial Multipliers Array Multipliers

19. Pipelined vs. Digit-Serial Multiplier: Energy Throughput • Operation pipelined version of energy delay Ethput = P·tclk·tmin·δ Digit-serial Multipliers Array Multipliers

20. Pipelined vs. Digit-Serial Multiplier: Energy Density • Normalizes the amount of energy used to perform a single operation to the logic resources used Edensity = P·tclk/Area Digit-serial Multipliers Array Multipliers

21. Pipelined vs. Digit-Serial Multiplier: Clock Energy Increase • In contrasts to an ASIC, there is very little or no increase in clock energy as pipeline depths or digit sizes are increased Digit-serial Multipliers Array Multipliers

22. Conclusions and Future Work • Glitch power is often a significant percentage of total consumed power • Up to 76% in an array multiplier • Reducing glitching is essential for low power designs

23. Conclusions and Future Work • Pipelining is an effective way of reducing glitches • Digit-serial multiplier almost eliminates glitches • Reducing glitching by pipelining reduces power consumption • Up to 96% in an array multiplier

24. Conclusions and Future Work • More information that just raw power consumption is required for effective low-power designs • Different energy metrics can provide this extra information • A high-level synthesis tool can use this information to produce low power designs