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AND. OR. AND. Marc D. Riedel. Assistant Professor, ECE University of Minnesota. EE 5393: Circuits, Computation and Biology. From ad hoc to Systematic… . “ A Symbolic Analysis of Relay and Switching Circuits ,” M.S. Thesis , MIT, 1937.
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AND OR AND Marc D. Riedel Assistant Professor, ECE University of Minnesota EE 5393: Circuits, Computation and Biology
From ad hoc to Systematic… “A Symbolic Analysis of Relay and Switching Circuits,”M.S. Thesis, MIT, 1937 “A Mathematical Theory of Communication,” Bell System Technical Journal,1948. Claude E. Shannon1916 –2001 Basis of all digital computation. Basis of information theory, coding theoryand all communication systems.
Building Digital Circuits Intel 4004(1971) ~2000 gates Intel “Nehalem”(2008) ~2 billion gates
Boxes inside Boxes [inside boxes…] 2000 transistors(Intel 4004, 1971) 800 million transistors(Intel Penryn, 2007) 1 transistor (1960’s)
From Chips to Computers IBM’s Blue Gene: 64,000 Processors
The Computational Landscape “There are known ‘knowns’; and there are unknown ‘unknowns’; but today I’ll speak of the known ‘unknowns’.” – Donald Rumsfeld, 2002 • Abutting true physical limits. • Cost and complexity are starting to overwhelm. Semiconductors:exponentially smaller, faster, cheaper – forever?
circuit Integrated Circuits inputs outputs 0 1 1 0 1 1 0 0 0 1 • What do integrated circuits do? • accept zeros and ones as inputs; • produce zeros and ones as outputs.
circuit Integrated Circuits inputs outputs 0 1 1 0 1 1 0 0 0 1 • Why do we want this? • zeros and ones represent information; • circuit performs computation.
circuit Integrated Circuits inputs outputs 0 1 1 0 1 1 0 0 0 1 • How do we build (design) such circuits? • hierarchically, from components.
inputs outputs … … . . . digital circuit … Building Digital Circuits • Design is driven by the input/output specification. • CAD tools are not part of the design process; they are the design process.
One made-up fact… [well, an abstraction really…] A Logic Gate
0 0 0 1 1 0 1 1 Logic Gates Common Gate: “AND” gate 0 0 0 1
Logic Gates Common Gate: “OR” gate 0 0 0 0 1 1 1 0 1 1 1 1
Logic Gates Common Gate: “NAND” gate 0 0 1 0 1 1 1 0 1 1 1 0
Logic Gates Common Gate: “NOR” gate 0 0 1 0 1 0 1 0 0 1 1 0
Logic Gates Common Gate: “XOR” gate 0 0 0 0 1 1 1 0 1 1 1 0
w x 1 1 w x 2 2 w ... 0 w x n n Linear Threshold Gates
Linear Threshold Gates Useful Model?
inputs outputs circuit Digital Circuit
inputs outputs circuit gate Digital Circuit
NAND OR AND AND NOR AND Memoryless Circuits Acyclic (i.e., feed-forward)circuits are always memoryless. 1 1 0 1 0 0 0 1 0 1 1 1
1 1 0 NAND 1 0 OR 0 0 1 AND AND 0 1 NOR 1 1 AND Memoryless Circuits Acyclic (i.e., feed-forward)circuits are always memoryless. Are memoryless circuits always acyclic? “Memoryless networks can never have feedback loops.” “A memoryless circuit is a directed acyclic graph (DAG)...”
Memoryless Circuits Acyclic (i.e., feed-forward)circuits are always memoryless. Are memoryless circuits always acyclic? “Memoryless networks can never have feedback loops.” “A memoryless circuit is a directed acyclic graph (DAG)...” Designers and EDA tools follow this practice.
AND OR AND OR AND OR Circuits with Cycles x a = + + + f b ( a x ( d c ( x f ))) 1 1 b x c d
Circuits with Cycles 0 0 x AND a OR = + + + 0 0 f b ( a x ( d c ( x f ))) 1 1 b AND 0 x OR c AND d OR
Circuits with Cycles 0 0 x AND a OR = + + + f b ( a x ( d c ( x f ))) 1 1 b AND 0 x OR c AND d OR
Circuits with Cycles 1 x AND a OR = + + + 1 1 f b ( a x ( d c ( x f ))) 1 1 b AND 1 1 x OR c AND d OR
Circuits with Cycles Circuit is cyclic yet memoryless; computes functions f1 and f2 with 6 gates. 1 x AND An acyclic circuit computing these functions requires 8 gates. a OR = + + f b ( a x ( d c )) 1 b AND 1 1 x OR c AND = + + f d c ( x b a ) 2 d OR
Circuits with Cycles Circuit is cyclic yet memoryless; computes functions f1 and f2 with 6 gates. There is no feedback in a functional sense. x A cyclic topology permits greater overlapin the computation of the two functions: AND An acyclic circuit computing these functions requires 8 gates. a OR = + + f b ( a x ( d c )) 1 b AND x OR c AND = + + f d c ( x b a ) 2 d OR
Computing with Feedback Theory • Formulate a precise model for analysis. • Provide constructions and lower bounds proving thatcyclic designs can be more compact. Practice • Devise efficient techniques for analysis and synthesis. • Implementthe ideas and demonstrated they are applicable for a wide range of circuits.
Theory Strategy: • Exhibit a cyclic circuit that is optimalin terms of the number of gates, say with C(n) gates, for n variables. • Prove a lower bound on the size of an acyclic circuit implementing the same functions, say A(n) gates. Main Result:
Cost 37 Acyclic circuit Always memoryless Cyclic circuit Cost 34 Memoryless Cyclic circuit Not memoryless Cost 30