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Pulse-Width Modulated DAC

Pulse-Width Modulated DAC. Lecture 11.3 Section 11.5. 8-Bit Counter. Pulse-Width Modulation. MODULE pwm " pulse-width modulated signal “ DECLARATIONS "Functional Blocks " div16cnt interface ([CLK,clear,count] -> [Q3,Q2,Q1,Q0,Cout]); cnt1 FUNCTIONAL_BLOCK div16cnt;

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Pulse-Width Modulated DAC

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  1. Pulse-Width Modulated DAC Lecture 11.3 Section 11.5

  2. 8-Bit Counter

  3. Pulse-Width Modulation

  4. MODULE pwm " pulse-width modulated signal “ DECLARATIONS "Functional Blocks " div16cnt interface ([CLK,clear,count] -> [Q3,Q2,Q1,Q0,Cout]); cnt1 FUNCTIONAL_BLOCK div16cnt; cnt2 FUNCTIONAL_BLOCK div16cnt; " Input Pins " Clock PIN 9; " 4 MHz clock SW7..SW0 PIN 11,7,6,5,4,3,2,1; " Switches 1..8 SW = [SW7..SW0]; " 8-bit high time " Output Pins " LED9 PIN 35 ISTYPE 'com'; " PWM output -- LED9 LED10 PIN 36 ISTYPE 'com'; " !PWM output -- LED10

  5. " Intermediate Nodes " Q7..Q0 NODE ISTYPE 'com'; " Clock divider Q = [Q7..Q0]; P NODE ISTYPE 'com'; notP NODE ISTYPE 'com'; set NODE ISTYPE 'com'; " Definitions " reset = (Q == SW); " equality detector

  6. EQUATIONS cnt1.clear = 0; " Clock divider cnt2.clear = 0; cnt1.CLK = Clock; cnt2.CLK = Clock; cnt1.count = 1; cnt2.count = cnt1.Cout; [Q7..Q4] = cnt2.[Q3..Q0]; [Q3..Q0] = cnt1.[Q3..Q0]; set = cnt2.Cout; " set every Q7 period P = !(reset # notP); " S-R latch notP = !(set # P); LED9 = P; LED10 = notP; END pwm

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