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Distributed Computation: Circuit Simulation

Distributed Computation: Circuit Simulation. CK Cheng UC San Diego ckcheng@ucsd.edu. Trends of Scaling (Moore’s Law). Expansion of applications: ai , bioinf , graphics, vision Explosion of communication: internet Distributed system: exascale computation

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Distributed Computation: Circuit Simulation

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  1. Distributed Computation: Circuit Simulation CK Cheng UC San Diego ckcheng@ucsd.edu

  2. Trends of Scaling (Moore’s Law) • Expansion of applications: ai, bioinf, graphics, vision • Explosion of communication: internet • Distributed system: exascale computation • Power constrained designs: low power • Interconnect dominance: VLSI • Nano-devices with variations: fault tolerant design, design for manufacturability Application System Technology

  3. Research Outline • Parallel SPICE • Cluster Machines • Netlist Partitioning • Whole Chip Analysis • SPICE Accuracy • Power Ground Analysis • Worst Power Load Exploration • 3D Power Distribution • Voltage Drop and Electronic Migration Analysis • RLC Optimization

  4. Circuit Simulation: Motivation • Technology Scaling • Challenges for Circuit Simulation • Complexity • Signal Integrity: crosstalk, voltage drop, coupling noise etc. • High clock frequency: Inductance Effect • Smaller transistors: Higher nonlinearity

  5. Simulation: Goal • Analyze whole chip with 100x memory capacity, 100x speed up, 100x efficiency for designers • Set standard of input/output for parallel processing • Allow cluster machines or cloud computing for the acceleration • Demonstrate the results via power ground analysis and teraHertz circuitry

  6. PUk-1 PU1 PU2 Direct Solver (KLU) Direct Solver (KLU) Direct Solver (KLU) Device Loading Device Loading Device Loading Equivalent Ckt Equivalent Ckt Equivalent Ckt Equivalent Ckt Equivalent Ckt Equivalent Ckt Linear-Nonlinear Iteration Interface PUK+j1 PUK PUK+jm Parallel AMG Parallel AMG Parallel AMG Parallel Device Loading (continued) PU: Processing Unit Nonlinear Sub-circuit … Nonlinear Sub-circuit Nonlinear Sub-circuit Original Circuit … linear Sub-circuit linear Sub-circuit linear Sub-circuit

  7. Action Items • Input/Output Parsing and Screening • Parallel Input • Parallel input format • Parallel parsing • Netlist Transformation • Parallel Output • Output parsing • Graphic display • Device Evaluation • Transistor Model • Matrix Solver • Sensitivity Calculation • Adaptive Time Step Control • Parallelization • Overall Framework • Implement in C/C++ • Which math library? • Sparse matrix library? • Parallel Implementation • Applications • Power Ground Network Analysis • Tera Hertz Circuit Simulation

  8. Power Grid Analysis • Package: • Voltage regulator • distributed RLC model • Silicon Chips: • Bumps • Metal wires

  9. Power Network Analysis: Motivation ITRS Roadmap: MPU

  10. Responses in Frequency Domain γ=1 γ=0 γ=0.05 T1 T2

  11. Time Domain Responses: Rogue Waves

  12. Conclusion • Spice Simulation for Whole System • Memory Capacity • CPU Time • User Interface • Power Distribution Analysis • Huge Netlist • Complex Electrical Behavior • Stringent Constraints

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