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Design and System Drivers - 2009 Worldwide Design ITWG Key actions / messages:

Design and System Drivers - 2009 Worldwide Design ITWG Key actions / messages:. Software, system level design productivity critical to roadmap 2. Initiated reliability / resilience roadmap 3. System-level design technology is key to power efficiency

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Design and System Drivers - 2009 Worldwide Design ITWG Key actions / messages:

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  1. Design and System Drivers - 2009Worldwide Design ITWGKey actions / messages: • Software, system level design productivity critical to roadmap • 2. Initiated reliability / resilience roadmap • 3. System-level design technology is key to power efficiency • 4. Design cost will be contained through innovation

  2. Overview (2004-9)1. Increasingly quantitative roadmap2. Increasingly complete driver set 2009 More Than Moore extension + iNEMI synch + SW !! 2008 More Than Moore extension + iNEMI + SW !! 2007 More Than Moore analysis + iNEMI Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Consumer Stationary, Portable Drivers 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Explore Design metrics Design Chapter

  3. ITRS Cost Chart 2009 (Millions of Dollars) RTL Functional Verif. Tool Set System Design Automation Transaction Level Modeling IC Implementation Tool Set Executable Specification AMP Parallel Processing SMP Parallel Processing Very Large Block Reuse Many Core Devel. Tools Transactional Memory Intelligent Testbench

  4. System Level Design & SOFTWARE • Hardware design productivity is growing appropriately • Requirements correspond roughly with solutions • Innovations pacing properly (transistors / designer / year) • Large gap in software productivity possibly opening up • If hardware accelerators are heavily leveraged, problem mitigated • Otherwise, possibly 100X gap can affect memory size, other • Adding new parameters to requirements/solutions tables • Hardware design productivity - requirement • Software design productivity - requirement • Software design productivity (assuming only software implementation) • System design productivity innovations – solutions (Fig. 1 in chapter) (alternative Scenario)

  5. Impact of Design on PowerEmphasis on System Level [SW/HW]

  6. Design and System Drivers - 2010Worldwide Design ITWGKey actions / messages: • Continue expanding importance of SW and system level • Quantify design technology impact on variability, “sigma” control in process • Update “design cost control through innovation” chart • 4. Develop design technology roadmap for 3D / TSV • 5. Develop new set of Design requirements/solutions from MtM • 6. Complete reliability roadmap for 2011

  7. Impact of Design on “Sigma” (Variability) • Goal • Quantify “how many sigmas” can design “reduce” • Approach • Inventory of design techniques / tools • Match inventory to parameters or correlations in model • Use variability model to capture “delta” in sigmas System / SW Check overall variation Logic / function Circuit Device Use variability model Manufacturing Inputs (manufacturing)

  8. More Than Moore (Design) • More than Moore brings new set of requirements/solutions • Will create additional inventory of parameters Existing requirements Existing solutions Existing Additional requirements Additional solutions Additional • E.g. • System-level (packaging) • Circuit (inter-chip parasitics modeling/simulation) • Layout (SiP global layout) • DFM (package-chip, SiP DFM)

  9. Design and System Drivers 2009Worldwide Design ITWGKey actions / messages: • Design update to ORTCs: SRAM, logic, defect density models • 2. Updated key system drivers: SOC-Consumer Portable, MPU • 3. Frequency-power envelope remains critical for industry • 4. Updated System Drivers, no new drivers • Expanded cross-TWG and public activity (DAC ’09 workshop)

  10. Overview (2004-9)1. Increasingly quantitative roadmap2. Increasingly complete driver set 2009 More Than Moore extension + iNEMI synch + SW !! 2008 More Than Moore extension + iNEMI + SW !! 2007 More Than Moore analysis + iNEMI Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Consumer Stationary, Portable Drivers 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Explore Design metrics Design Chapter

  11. ORTCs: New A-Factor Models(Area = A-factor  F2) Logic: A-factor = 175 NAND2 Area = 3 PPoly  8 PM2 (3 1.5 PM1)  (8  1.25 PM1) = 45 (PM1)2 = 180 F2 175 F2 SRAM: A-factor = 60 SRAM Bitcell Area = 2 PPoly 5 PM1 = 3 PM1  5 PM1= 15 (PM1)2 = 15 (2 F)2 = 60F2 M2 pitch (PM2 1.25PM1) NWell Active Poly Contact M1 Contacted-poly pitch (PPoly 1.5PM1) M1 pitch (PM1) Contacted-poly pitch (PPoly 1.5PM1) Fitted to industry data

  12. Key System Drivers Constantly UpdatedConsumer Driver Model • 2008: Updated power model with realistic dynamic power • Memory dynamic power 10X less than modeled previously • Will identify key driver requirements, explore coloring • E.g., excessive power beyond portable limit (1 W  0.5W) • Exploring RF/A/MS for future portable consumer drivers • Extends existing driver (or, future “wireless” driver is possible) • Exploring additional parameters per Test requests • #clocks, #power domains, #unique cores, #IOs, etc. 4.3 W max total (2022) 8 W max total (2022)

  13. SOC Consumer Portable Architecture Model (updated) Main Prc. Main Prc. PE-1 PE-2 … PE-n Main Prc. Main Prc. Main Memory Main Prc. Main Prc. PE PE PE Main Memory Main Prc. Main Prc. PE PE PE Peripherals PE PE PE Peripherals PE PE PE Function A Function B Function C Function D Function E PE PE - #Main Processors grows to 2, 4 and beyond - Power budget reduced to 0.5W - Die size reduces slowly to 44mm2

  14. Updated MPU Density/Power/Frequency M1 Half-Pitch (F) Physical Lgate (L) Decrease Pdyn and Pleak Increase Pdyn , decrease Pleak Growth of #Tr 2x / 3 year (WAS)  2x / 2 year (IS) up to 2013 Die size reduction 310mm2 (WAS)  260mm2 (IS) Unit cell size A-Factor (A) Logic: ~320 (WAS) 175 (IS) SRAM: ~100 (WAS) 60 (IS) #core/die, #tr/core 12.2% / year (WAS)  18.9% / year (~2013, IS),  12.2% / year (2014~, IS) Increased Pdyn and Pleak

  15. Design Pacing, Challenges Unabated 2009: Final Lgate and M1 HP scaling impact on Drivers Physical Lgate M1 Half Pitch 2 year delay, but faster scaling 0.7x / 3yr  0.7 / 2yr (~2013), 0.7x / 3yr (2014~) Updated MPU model (power) 1 year shift #Tr per die New A-factors Faster M1 half pitch reduction

  16. Frequency-Power Envelope Remains Critical System Issue • Current priorities • Power #1 goal • Frequency slowdown • Multi-core enables tradeoff • Need to track trade-off • Market vigilance • Yearly adjustment • Possible 2009 survey 7.7% / year ~2013: 18.9% / year 2014~: 12.2% / year

  17. DAC-2009 Roadmapping WorkshopSan Francisco, July 27, 2009 9am – 3pm 35 Attendees • 9:15am - 10:00am Plenary • The ITRS Semiconductor Industry Roadmap --- Alan K. Allan (Intel) • 10:00am - noon Session I: EDA Roadmaps and Perspectives • The CATRENE (Europe) EDA Roadmap --- W. Rosenstiel (U. Tubingen) • The STRJ/WG1 (Japan) EDA Roadmap --- (STRJ representative) • The ITRS Design / System Drivers Roadmap – Carballo/Kahng (ITRS) • Synopsys Roadmap Perspective --- A. Domic (Synopsys) • Cadence Roadmap Perspective --- D. Noice (Cadence) • Mentor Roadmap Perspective --- R. Hum (Mentor) • Design Technology Coalition Perspective --- J. Darringer (IBM) • SI2 Perspective --- S. Dasgupta (SI2) • Mini-Panel Discussion: "Can We Roadmap EDA? For whom?” • Noon - 1:30pm: Creating the Right EDA Industry Roadmap

  18. Design and System Drivers 2010Worldwide Design ITWGKey actions / messages: • Update key system drivers: SOC-Consumer Portable, MPU • Update frequency-power MPU roadmap • Continue to broaden System Drivers, but more cautiously • Develop new “MtM” System Driver parameters, “SIP fabric” • Continue cross-TWG and public activity (DAC2010 workshop) • Maintain iNEMI relationship/linkage around portable driver

  19. New System Drivers? At the right pace… • New SIP Fabric driver effort started in 2009 • Others (aerospace & defense, medical, auto, FPGA) deferred 2010? 2010? 2007 2006 2006 2006 2010? Fabrics MPU SIP PE/DSP Memory AMS Markets Consumer Stationary Consumer Portable Medical Automotive Network Office A&D

  20. More Than Moore Brings Alternative Set of Parameters (2010-) • Will create additional inventory of parameters CONCEPT: Current SoC scenario vs. Additional SiP scenario Consumer portable (SoC) Consumer portable (SiP) Power System Drivers Normalized Cost Consumer stationary (SoC) Consumer stationary (SiP) Performance System Drivers Normalized Cost

  21. System Drivers and iNEMI (2009)Proposal to iNEMI: develop Portable System Architecture TemplateNew Chair with domain expertise – expect deeper commitment Application processor Baseband processor Processing POWER Memory NAND Flash Memory Wireless Flash Memory / Flash COST Other (MEMS, etc.) Audio / video codec Power mgt. I/O controller I/O transceivers Analog / I/O NOISE SENSITIVITY

  22. Design & Key ITRS Cross-TWG Initiatives With Interconnect (A&P): 3D / TSV roadmapping survey With PIDS, FEP, IRC: Power-driven roadmap; modeling and requirements support for CV/I  RO-based transistor metric With CSTNSG: Updated frequency, SRAM area, active area (yield) projects With More Than Moore Study Group: Definition of SIP-scenario System Driver roadmaps to complement existing SOC-scenario Driver roadmaps

  23. Summary Design Actions 2010 • Continue expanding importance of SW and system level • Quantify design tech. impact on variability / “sigma” control • 3. Update “design cost control through innovation” chart • 4. Develop design technology roadmap for 3D / TSV • 5. Develop new set of Design requirements/solutions from MtM • 6. Complete reliability roadmap for 2011 System Drivers Actions 2010 • Update key system drivers: SOC-Consumer Portable, MPU • Update frequency-power MPU roadmap • Continue to broaden System Drivers, but more cautiously • Develop new “MtM” System Driver parameters, “SIP fabric” • Continue cross-TWG and public activity (DAC2010 workshop) • Maintain iNEMI relationship/linkage around portable driver

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