Early output logic and Anti-Tokens

1. Early output logic and Anti-Tokens Charlie Brej APT Group Manchester University

2. Overview • Synchronous Problems • Asynchronous Logic • Why? • How? • Solutions • Early Output • Anti-Tokens

3. Problems: Communication • Communication horizon • “For a 60 nanometer process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997] • Clock distributed using wave pipelining

4. Problems: Performance Unbalanced Stages Clock overheads Clock Skew/Jitter Transistor Variability Timing Assumption overheads Signal Integrity Cycle time Worst – Average case performance Real Computation

5. Clock! What is it good for? • No arguing with the clock • 9am - 5pm. No excuses!

6. Bundled-Data • When you finish, do the next task • Flexitime Request + Delay Acknowledge

7. How do you know when you are finished? • Synchronous: • Estimate • Global timing reference • Asynchronous (bundled-data) • Estimate • Local delay elements • Asynchronous (delay-insensitive) • When the data arrives • Intrinsic

8. Becoming Delay Insensitive • Dual-Rail • Two wires • 00 – NULL • 01 – Zero • 10 – One • (11 – Not used) • Four Phase handshake • Return to zero R0 R1 Ack

9. Dual-Rail interfaces Output generated as early as possible Two Early output cases If either input is ‘0’ then the output is ‘0’ Early Output Logic

10. Bit level pipelining • Forward completed parts of the result • Pace work • Don’t stall parts unless you have to

11. Bit level pipelining • Forward completed parts of the result • Pace work • Don’t stall parts unless you have to

12. Bit level pipelining • Forward completed parts of the result • Pace work • Don’t stall parts unless you have to

13. Early Output cases

14. Validity • Unnecessary late inputs • Must be acknowledged • Must wait until they arrive • Validity signal • Latch generated • Ready to be acknowledged • Result before all inputs present • Acknowledge after all inputs present

15. Synchronisation Hurts • No need to wait before generating result • Need to wait for input in order to acknowledge it • Unnecessary stall

16. Anti-Tokens • Unnecessary late inputs • Stall the entire stage • Proactive approach • Send a ‘cancel’ signal backward to the source • Acknowledge before data arrives • Anti-Token latches • Assert validity early

17. Anti-token generation 0 1 C

18. Anti-token generation 0 1 A C

19. Anti-token Propagation 1 A C

20. Anti-token Propagation 1 A A C

21. Anti-token Token collisions A A 1 1 A A 1 1 ? 1 A ?

22. Anti-token Token collisions 1 A A 1 1 A A 1 1 1 1 1

23. Remove Unnecessary computation Unbalanced Stages Clock overheads Clock Skew/Jitter Transistor Variability Timing Assumption overheads Signal Integrity Worst – Average case performance Unnecessary Computation/Delays Real Computation Cycle time

24. Summary • Asynchronous • Delay Insensitive • Safe • No timing assumptions • Average case performance • Remove unnecessary computation • Anti-tokens without mutual exclusion units