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Network-on-Chip benchmarking workgroup, status update

Network-on-Chip benchmarking workgroup, status update. March 2012, Erno Salminen. Recent activities. Released a SystemC DRAM model New release of Transaction Generator Benchmarking of EEMBC MultiBench Chapter in OCP book Our benchmarks aim to answer two basic questions:

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Network-on-Chip benchmarking workgroup, status update

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  1. Network-on-Chip benchmarking workgroup, status update March 2012, Erno Salminen

  2. Recent activities Released a SystemC DRAM model New release of Transaction Generator Benchmarking of EEMBC MultiBench Chapter in OCP book Our benchmarks aim to answer two basic questions: NoC developer: What gain does my novel feature bring? System integrator: Which NoC should I choose and how should I configure it? Download the materials from http://www.ocpip.org 2

  3. Accurate Dynamic Random-Access MemoryModel (ADM) package • DRAM performance is essential to the whole system • Drastic difference between best case and more realistic one (see the figure) • E.g. 99.7% efficiency in best case vs. more realistic 44.3% • t_wtr = write-to-read delay, e.g. 7.5 ns • t_rc = row activation delay, e.g. 55ns • t_rp = closing a page, e.g. 10ns

  4. ADM package (2) • ADM package was developed by Royal Institute of Technology (KTH), Sweden • SystemC, LGPL, OCP-IP TLM Kit • Performance impact has been evaluated • ADM, Noxim, Simics, GEMS, Ruby, SPLASH-2 • Even an order of magnitude difference in latency compared to simplistic DRAM model • Report and conference article being prepared • Free download from http://www.ocpip.org/memory_model.php

  5. Transcation Generator • Tool for evaluting MP-SoCs and NoCs • Executes a data-flow model of the workload • SystemC, LGPL, OCP-IP TLM kit • New features • Includes a set of 9 application models • Integrates accurate DRAM model • Able to run MCSL benchmarks as well • GUI helps visualizing the simulation results • Free download from http://www.ocpip.org/tg_package.php

  6. The concept of Transcation Generator

  7. Set of application models

  8. Set of application models (2) • [Esko Pekkarinen, Lasse Lehtonen, Erno Salminen, Timo D. Hämäläinen, "A Set of Traffic Models for Network-on-Chip Benchmarking", International Symposium on System-on-Chip, Tampere, Finland, October 31, 2011 - November 2, 2011, pp. 78-81.]

  9. Example of added DRAM accesses Timer 0 PE 0 DRAM PE 1 Task graph Mapping HW platform 1. Cache miss during task A execution. Only 1 shown here timer 0 Processing element 0 Task A Mem region Z simulate 2 Task B loads source data from mem before ”proces-sing” DRAM Noc Task B Processing element 1 3 Task B writes result data to mem … XML … … … …

  10. TG + MCSL example ./sctg.exe -i examples/sparse_mesh_8x8.stp -c examples/constraints.xml Transaction Generator input-file: examples/sparse_mesh_8x8.stp Delay for playback: 1ms Directory to save logs: . cpu0: int (1) float (1) mem (1) . . . Task task_0 mapped to PE cpu0 . . . NocFactory class: mesh_2d Starting simulation with seed 42 Measuring statistics with 1 ms interval Measuring. Current simulation time is 1 ms Measuring. Current simulation time is 2 ms . . . Simulation ends at 100 ms Table: [Weichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang, Mahdi Nikdast, Zhehui Wang, “A NoC Traffic Suite Based on Real Applications,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2011. Available: http://www.ece.ust.hk/~eexu/publications/ISVLSI2011_Benchmark.pdf]

  11. EEMBC Multibench profiling • MultiBench™ is a suite of embedded benchmarks that allows processor and system designers to analyze, test, and improve multicore architectures and platforms. • http://www.eembc.org/benchmark/multi_sl.php • Profiling carried out in Univ. Boston • Applications running in M5 system simulator • 1 to 64 Alpha cores, input set size 4M • Report being prepared

  12. Book chapter • A book called Introduction to Open Core Protocol: Fastpath to System-on-Chip Design is to appear • Edited by W. David Schwaderer, published by Springer • More reader-friendly introduction to OCP than the full specification • Includes numerous, real “usage examples” and integrates coverage of design methodology • Includes also Chapter 13- Benchmarking Network-on-Chip (NoC) Designs • More info at http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4614-0102-5

  13. Near-future activities • Provide example results for existing benchmarks for TG • New users can check that their TG installation works • Users get rough idea of expected results • Publish reports on ADM and Multibench • Finding more benchmarks and develop tools further • Suggestions are welcome! • Contact admin@ocpip.org

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