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NOCARC Network on Chip Architecture

KTH, VTT Nokia, Ericsson, Spirea TEKES, Vinnova. NOCARC Network on Chip Architecture. Outline. NoC Architecture overview Activities Switch Design Buffer-less Hot-potato routing Stress sensitive routing. NoC Architecture Overview. Switch. Resource.

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NOCARC Network on Chip Architecture

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  1. KTH, VTT Nokia, Ericsson, Spirea TEKES, Vinnova NOCARCNetwork on Chip Architecture Axel Jantsch

  2. Outline • NoC Architecture overview • Activities • Switch Design • Buffer-less • Hot-potato routing • Stress sensitive routing Axel Jantsch

  3. NoC Architecture Overview Switch Resource • Message passing communication infrastructure • Physical-Architectural Level design integration Axel Jantsch

  4. Resource-Network Interface RNI Resource Axel Jantsch

  5. Concept of Region • Resources larger than a slot • FPGA • Memory • Parallel processor • Wrapper will make the region transparent to outside traffic • Communication within a region could happen differently than rest of the network Wrapper Axel Jantsch

  6. Quick Summary of Activities • NoC Architecture Implementation • Physical feasibility study • Buffer Less Switch Design • NoC Evaluation • Ns-2 based NoC Simulator • Dedicated simulator for NoC • Nostrum protocol stack • 5-layered protocol stack • Two Phase Design Methodology • Special Purpose NoC Region • NoC Specific Fault Model and Error Protection • NoC Specific Quasi-synchronous Clocking Axel Jantsch

  7. Buffer Less Switch Packet Packet Packet Packet Switch Packet Packet Packet Packet Axel Jantsch

  8. Load distribution using Stress values • Load information sent between switches, stress value • no Stress value • with Stress value • averaged Stress value (four cycles) • Better routing decisions for intermediate load • Larger design Axel Jantsch

  9. Final implementation Axel Jantsch

  10. Results of synthesis (using Synopsys) Axel Jantsch

  11. Maximum probability for various mesh sizes Axel Jantsch

  12. Network delay Axel Jantsch

  13. Number of packets in centre FIFO p=0.47 p=0.48 p=0.49 p=0.50 Axel Jantsch

  14. Average load in FIFOs with no Stress value max=3.2 Axel Jantsch

  15. Average load in FIFOs using Stress value max=0.9 Axel Jantsch

  16. Average load in FIFOs using averaged Stress value max=0.15 Axel Jantsch

  17. times longer waiting time Comparing results max=0.9 max=0.15 max=3.2 Axel Jantsch

  18. Conclusion • A buffer-less switch is feasible • Very low cost and high performance • Stress values is a simple control mechanism • It increases maximum load by 20% • It decreases the maximum latency by factor of 20 Axel Jantsch

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