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Operation Regions of Bipolar Transistors

Operation Regions of Bipolar Transistors. Binary Logic States. Digital Logic:. Bipolar transistor as an inverter. Transistor in digital logic pass quickly from the off region to the saturation region. Input Output 1(high V in ) 0(low input) 0 1.

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Operation Regions of Bipolar Transistors

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  1. Operation Regions of Bipolar Transistors Binary Logic States

  2. Digital Logic: Bipolar transistor as an inverter • Transistor in digital logic pass quickly from the off region to the saturation region. Input Output 1(high Vin) 0(low input) 0 1

  3. Bipolar NOR logic gate Example 3.11 Determine current and voltage in the circuit 3.43(b) Rc=1K RB=20K VBE(on)=0.7V VCE(sat)=0.2V β=50 Lecture #3

  4. Biasing for BJT • Goal of biasing is to establish known Q-point which in turn establishes initial operating region of the transistor. • For a BJT, the Q-point is represented by (IC, VCE) for an npn transistor or (IC, VEC) for a pnp transistor. • The Q-point controls values of diffusion capacitance, transconductance, input and output resistances. • In general, during circuit analysis, we use simplified mathematical relationships derived for a specified operation region, and the Early voltage is assumed to be infinite. • Two practical biasing circuits used for a BJT are: • Four-Resistor Bias network • Two-Resistor Bias network

  5. The process by which the quiescent output voltage is caused to fall somewhere the cutoff and saturated values is referred to as biasing.

  6. Example 3.13

  7. Q-point has shifted Substantially. Q-point is not stabilized Against the variation .

  8. Tolerances - Worst-Case Analysis: Example • Problem: Find worst-case values of IC and VCE. • Given data: bFO = 75 with 50% tolerance, VA = 50 V, 5 % tolerance on VCC , 10% tolerance for each resistor. • Analysis: To maximize IC , VEQ should be maximized, RE should be minimized and opposite for minimizing IC. Extremes of RE are: 14.4 kW and 17.6 kW. To maximize VEQ, VCC and R1 should be maximized, R2 should be minimized and opposite for minimizing VEQ.

  9. Tolerances - Worst-Case Analysis: Example (cont.) Extremes of VEQ are: 4.78 V and 3.31 V. Using these values, extremes for IC are: 283 mA and 148 mA. To maximize VCE , IC and RC should be minimized, and opposite for minimizing VEQ. Extremes of VCE are: 7.06 V (forward-active region) and 0.471 V (saturated, hence calculated values for VCE and IC actually not correct).

  10. BJT SPICE Model • Besides capacitances associated with the physical structure, additional components are: diode current iS and substrate capacitance CJS related to the large area pn junction that isolates the collector from the substrate and one transistor from the next. • RB is resistance between external base contact and intrinsic base region. • Collector current must pass through RC on its way to active region of collector-base junction. • RE models any extrinsic emitter resistance in device.

  11. BJT SPICE Model Typical Values Saturation Current IS = 3x10-17 A Forward current gain BF = 100 Reverse current gain BR = 0.5 Forward Early voltage VAF = 75 V Base resistance RB = 250 W Collector Resistance RC = 50 W Emitter Resistance RE = 1 W Forward transit time TT = 0.15 ns Reverse transit time TR = 15 ns Chap 5 - 34

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