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Chapter 4

Chapter 4. Input/Output Organization. Processor. Memory. Bus. I/O de. vice 1. I/O device n. Figure 4.1. A single-bus structure. Memory-mapped I/O. Input and output buffers use same address space as memory locations All instructions can access the buffers

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Chapter 4

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  1. Chapter 4 Input/Output Organization

  2. Processor Memory Bus I/O de vice 1 I/O device n Figure 4.1. A single-bus structure.

  3. Memory-mapped I/O • Input and output buffers use same address space as memory locations • All instructions can access the buffers • Move DATAIN, R0 Read from keyboard buffer • Move R0, DATAOUT Send to display buffer • DATAIN, DATAOUT: addresses of keyboard and display buffers

  4. Isolated I/O • Separate address space for I/O devices • Special instructions (e.g., IN, OUT) that indicate that the address is not in memory address space • Intel processors can use either

  5. Using the “Address Space” • Move R0, DATAOUT • OUT R0, DATAOUT If memory-mapped, then DATAOUT (say address 123) refers to the display buffer, same address as a memory location If isolated then DATAOUT (say address 123) refers to the display buffer, and memory location 123 is not used for this

  6. Address lines Bus Data lines Control lines Address Control Data and I/O decoder circuits status registers int erface Input device Figure 4.2. I/O interface for an input device.

  7. D A T AIN D A T A OUT KIRQ SOUT SIN ST A TUS DIRQ KEN CONTR OL DEN 7 6 5 4 3 2 1 0 Figure 4.3. Registers in keyboard and display interfaces

  8. Move #LINE, R0 Initialize memory pointer WAITK TestBit #0, STATUS Test SIN Branch=0 WAITK Wait for character to be entered Move DATAIN, R1 Read the character WAITD TestBit #1, STATUS Test SOUT Branch=0 WAITD Wait for the display to become ready Move R1, DATAOUT Send the character to the display Move R1, (R0)+ Store the character and advance the pointer Compare #$0D, R1 Check if the character is CR Branch=0 WAITK If not, get another character Move #$0A, DATAOUT Otherwise, send Line Feed Call PROCESS Call a subroutine to process the input line Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display.

  9. Interrupts • Interrupt-request line • Interrupt-request signal • Interrupt-acknowledge signal • Interrupt-service routine • Similar to subroutine • May have no relationship to program being executed at time of interrupt • Program info must be saved • Interrupt latency

  10. Program 1 Program 2 COMPUTE routine PRINT routine 1 2 Interrupt occurs i here i + 1 M Figure 4.5. Transfer of control through the use of interrupts.

  11. Handling Interrupts • Many situations where the processor should ignore interrupt requests • Interrupt-disable • Interrupt-enable • Typical scenario • Device raises interrupt request • Processor interrupts program being executed • Processor disables interrupts and acknowledges interrupt • Interrupt-service routine executed • Interrupts enabled and program execution resumed

  12. V dd Processor R I N T R INTR INTR1 INTR2 INTR n Figure 4.6. An equivalent circuit for an open-drain bus used to implement a common interrupt-request line.

  13. because it is active when in the low voltage state I N T R V dd Processor pull-up resistor R I N T R INTR INTR1 INTR2 INTR n inverter (NOT gate) INTR signal is low when interrupt line is high line voltage is high (=Vdd) when inactive

  14. because it is active when in the low voltage state I N T R V dd Processor R I N T R INTR INTR1 INTR2 INTR n inverter device n interrupts by closing switch, bringing line voltage down to 0 INTR signal is high when interrupt line is low line voltage is low (0) when active

  15. V dd Processor R I N T R INTR INTR1 INTR2 INTR n Figure 4.6. An equivalent circuit for an open-drain bus used to implement a common interrupt-request line.

  16. Handling Multiple Devices • How can the processor recognize the device requesting an interrupt? • How can the processor obtain the starting address of the appropriate interrupt-service routine? • Should a device be allowed to interrupt the processor while another interrupt is being serviced? • How should two or more simultaneous interrupt requests be handled?

  17. Interrupt Priority • Multi-level priority organization • During execution of interrupt-service routine • Disable interrupts from devices at the same level priority or lower • Continue to accept interrupt requests from higher priority devices • Privileged instructions executed in supervisor mode • Controlling device requests • Interrupt-enable • KEN, DEN

  18. I N T R 1 I N T R p Processor Device 1 Device 2 Device p INTA1 INTA p Priority arbitration circuit Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

  19. I N T R 1 I N T R p Processor Device 1 Device 2 Device p INTA1 INTA p Priority arbitration circuit Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines. Priority determined by the order in which processor accepts and acknowledges interrupts

  20. Polled interrupts: Priority determined by the order in which processor polls the devices (polls their status registers) Vectored interrupts: Priority determined by the order in which processor tells device to put its code on the address lines (order of connection in the chain) I N T R Processor Device 1 Device 2 Device n INTA (a) Daisy chain Figure 4.8.Interrupt priority schemes. Daisy chaining of INTA: If device has not requested service, passes the INTA signal to next device If needs service, does not pass the INTA, puts its code on the address lines

  21. I N T R 1 Device Device INTA1 Processor I N T R p Device Device INTA p Priority arbitration circuit (b) Arrangement of priority groups Figure 4.8.Interrupt priority schemes. Priority determined by the order in which processor accepts and acknowledges interrupts from a particular group

  22. Multiple Interrupts • Priority in Processor Status Word • Status Register -- active program • Status Word -- inactive program • Changed only by privileged instruction • Mode changes -- automatic or by privileged instruction • Interrupt enable/disable, by device, system-wide

  23. Main Program Move #LINE, PNTR Initialize buffer pointer Clear EOL Clear end-of-line indicator BitSet #2, CONTROL Enable keyboard interrupts BitSet #9, PS Set interrupt-enable bit in the PS … continue to process Interrupt Service Routine READ MoveMultiple R0-R1, -(SP) Push registers R0,R1 onto stack Move PNTR, R0 Load memory address pointer MoveByte DATAIN, R1 Get input character MoveByte R1, (R0)+ Store it in memory Move R0, PNTR Update memory pointer CompareByte #$0D, R1 Check if Carriage Return Branch NZ RTRN Move #1, EOL Indicate end-of-line BitClear #2, CONTROL Disable keyboard interrupts RTRN MoveMultiple (SP)+, R0-R1 Pop and restore registers Return Return from interrupt

  24. Main Program Move #LINE, PNTR Initialize buffer pointer Clear EOL Clear end-of-line indicator BitSet #2, CONTROL Enable keyboard interrupts BitSet #9, PS Set interrupt-enable bit in the PS Variable: Periodically checked by program to determine when line has been read 0 EOL KIRQ DIRQ IE PS 1 9 8 7 6 5 4 3 2 1 0 KEN DEN CONTROL 1 7 6 5 4 3 2 1 0

  25. Interrupt Service Routine READ MoveMultiple R0-R1, -(SP) Push registers R0,R1 onto stack Move PNTR, R0 Load memory address pointer MoveByte DATAIN, R1 Get input character MoveByte R1, (R0)+ Store it in memory Move R0, PNTR Update memory pointer CompareByte #$0D, R1 Check if Carriage Return Branch NZ RTRN Move #1, EOL Indicate end-of-line BitClear #2, CONTROL Disable keyboard interrupts RTRN MoveMultiple (SP)+, R0-R1 Pop and restore registers Return Return from interrupt Invoked each time the keyboard puts a character in DATAIN and causes an interrupt Continues until CR character encountered, then keyboard interrupts are disabled until another line is requested

  26. Interrupt Vectoring Interrupt Service Routine Address of ISR Memory Location Code Address Bus Device Interrupt Control Bus

  27. Common Functions of Interrupts • Interrupt transfers control to the interrupt service routine, generally through the interrupt vector table, which contains the addresses of all the service routines. • Interrupt architecture must save the address of the interrupted instruction and the contents of the processor status register. • Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt. • A software-generated interrupt may be caused either by an error or a user request (sometimes called a trap). • An operating system is interrupt driven.

  28. Interrupts Hardware interrupts—from I/O devices, memory, processor, etc. Software interrupts—generated by a program. Interrupts signal attention requests and error conditions. Interrupts may be intrinsic or user-defined. Other terms: Trap Fault Exception System call IRQ

  29. Interrupt Handling Interrupt Code Memory Location Interrupt Vector Table …00 Address of Timer ISR 0 software interrupt …31 Address of Disk Read ISR 31 Address of Disk Read Complete ISR …32 32 hardware interrupt Address of Print ISR …87 87 …137 Address of Invalid Instruction ISR 137

  30. Interrupt Handling • The operating system preserves the state of the CPU by storing registers and the program counter. • Determines which type of interrupt has occurred: • vectored interrupt system • Separate segments of code determine what action should be taken for each type of interrupt

  31. The Objective … write result read data write result read data P1: compute compute … write result read data write result read data P2: compute compute write result read data … write result read data P3: compute compute

  32. Diagram of Process StateMultiprogramming dispatch running exit ready admit terminated interrupt system call new program interrupt waiting waiting (for I/O, etc.)

  33. Process Scheduling Queues • Job queue – set if new programs presented to the system. • Ready queue – set of all processes residing in main memory, ready and waiting to execute. • Device queues – set of processes waiting for an I/O device. • Process migration between the various queues.

  34. Diagram of Process StateMultiprogramming Process 3 running ready terminated Process 4 Process 5 new program Ready Queue Process 1 Process 6 Process 9 Process 10 etc. Wait Queue(s) Process 2 Process 7 Process 8 Process 11 etc. waiting Job Queue Job A Job B Job C etc.

  35. Diagram of Process StateMultiprogramming Process 3 dispatch running ready exit admit interrupt (preempt) terminated system call, I/O or event wait new program interrupt, I/O or event completed Ready Queue Process 1 Process 6 Process 9 Process 10 etc. Wait Queue(s) Process 2 Process 7 Process 8 Process 11 etc. waiting Job Queue Job A Job B Job C etc.

  36. OSINT Set interrupt vectors: Time-slice clock SCHEDULER Software interrupt OSSERVICES Keyboard interrupts IOData . . . OSSERVICES Examine stack to determine requested operation Call appropriate routine SCHEDULER Save program state Select a runnable process (say process B) Restore saved context of new process Pop new values for PS and PC from stack Return from interrupt (resuming execution of B) Figure 4.10(a) OS Initialization, services and scheduler

  37. IOINIT Set process status to Blocked (Waiting) Initialize memory buffer address pointer and counter Call device driver to initialize device and enable interrupts in the device interface Return from subroutine IODATA Poll devices to determine source of interrupt Call appropriate driver If END = 1, then set process status to Runnable Return from interrupt Figure 4.10(b) I/O routines

  38. KBDINIT Enable interrupts Return from subroutine KBDDATA Check device status If ready, then transfer character If character = CR, then {set END = 1; Disable interrupts} else set END = 0 Return from subroutine Figure 4.10(c) Keyboard driver

  39. fast interrupt request disable Interrupt request disable Mode bits: Five privileged modes 7 6 5 4 3 2 1 0 I F M4 M3 M2 M1 M0 CPSR: Current program status register Figure 4.11. Low-order byte of the ARM processor status register.

  40. 15 13 10 8 4 3 2 1 0 T S X N Z V C T race Condition mode Codes Interrupt Supervisor Priority mode Figure 4.14. Processor status register in the 68000 processor .

  41. Trace interrupt enable Flag Interrupt enable Flag I/O Privilege Level 15 14 13 12 11 10 9 8 IOPL IF TF EFLAGS register Figure 4.16. Part of the Pentium's processor status register.

  42. Direct Memory Access (DMA) • Polling or interrupt driven I/O incurs considerable overhead • Multiple program instructions • Saving program state • Incrementing memory addresses • Keeping track of word count • Transfer large amounts of data at high speed without continuous intervention by the processor • Special control circuit required in the I/O device interface, called a DMA controller • DMA controller keeps track of memory locations, transfers directly to memory (via the bus) independent of the processor

  43. DMA Controller • Part of the I/O device interface • DMA Channels • Performs functions that would normally be carried out by the processor • Provides memory address • Bus signals that control transfer • Keeps track of number of transfers • Under control of the processor

  44. Direct Memory Access (DMA) • OS responds to a program’s system call for Disk Read, for example • OS puts the program in the “blocked” or “waiting” or “asleep” state • Initiates the Disk Read • Starts execution of another program • When Read is completed, DMA controller sends an interrupt

  45. 31 30 1 0 Status and control IRQ Done IE R / W Starting address W ord count Figure 4.18 Registers in a DMA interface Figure 4.18. Re gisters in a DMA interf ace.

  46. 31 30 1 0 0 1 1 Status and control IRQ Done IE R / W 42000 Starting address 1200 W ord count incremented each time a word is transferred Figure 4.18 Registers in a DMA interface Figure 4.18. Re gisters in a DMA interf ace.

  47. Main Processor memory System bus Disk/DMA DMA Printer K e yboard controller controller Netw ork Disk Disk Interf ace Figure 4.19. Use of DMA controllers in a computer system. Figure 4.19. Use of DMA controllers in a computer system.

  48. DMA • Processor and DMA controller(s) must “interweave” memory accesses • DMA controllers have higher priority for obvious reason, i.e., higher speed devices need higher priority

  49. DMA processor gets most cycles “cycle stealing” • If DMA gets a cycle at a time, then • CPU gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus) • DMA gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus)

  50. DMA • Or • CPU gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus) • DMA gets a memory cycle (uses bus) • DMA gets a memory cycle (uses bus) • DMA gets a memory cycle (uses bus) • DMA gets a memory cycle (uses bus) . . . • DMA gets a memory cycle (uses bus) • CPU gets a memory cycle (uses bus) “burst mode” to transfer a block of data without interruption

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