Linking the Components

2. 4 Linking the Components

3. Linking The Components • A computer is a system with data and instructions flowing between its components in response to processor commands. • In order to work, these components must be physically linked.

4. Linking the ComponentsThe Bus • Internal components are: • linked by a bus • A ribbon-like set of parallel wires that can carry several bits at a time in parallel. • Power • Instructions • Data • Addresses • Commands

5. Linking the ComponentsThe Bus • Types of Bus • Processor Bus • Delivers information to and from the processor • Memory Bus • Carries information between memory and the processor. • High-Speed I/O Bus • Links high-speed peripherals to the system. • Standard I/O Bus • Links slower devices to the system.A ribbon-like set of parallel wires that can carry several bits at a time in parallel.

6. Linking the ComponentsWord Size • Internal components are: • Designed around a common word size • Word size affects: • Processing Speed • 32-bit bus contains 32 parallel lines that can carry 32 bits at a time. • 16-bit bus contains 16 parallel lines that can carry 16 bits at a time. • The bigger the word size, the faster the computer.

7. Linking the ComponentsWord Size • Internal components are designed around a common word size: • Word size affects: • Memory Capacity • 32 bit address – 4 billion memory locations • 16 bit address – 64,000 memory locations • The bigger the word size – the more memory a computer can address.

8. Linking the ComponentsWord Size • Internal components are designed around a common word size: • Word size affects: • Precision • The number of significant digits a machine can address • Registers hold one word. • The processors internal circuitry is usually more efficient when manipulating numbers one word in length. • A 32 bit mainframe adds 32-bit numbers • A 16 bit machine adds 16-bit numbers • The bigger the word size, the more precise.

9. Linking the ComponentsWord Size • Internal components are designed around a common word size: • Word size affects: • Instruction set size • Instructions move from memory to the processor over a bus. • A 32 bit bus can carry a bigger instruction than a 16 bit bus. • The bigger instruction size means more bits are available for operation code.

10. Linking the ComponentsWord Size • Internal components are designed around a common word size: • Word size affects: • Cost • A bigger word size means: • a faster, more precise machine with greater memory capacity, • a larger, more varied instruction set, • a higher price tag.

11. Linking the ComponentsMachine Cycles • Instruction Time (I-time) • The instruction control unit fetches the next instruction from memory • The address of the next instruction is found in the instruction counter • The instruction control unit extracts this address and sends it over the bus to the memory controller • The memory controller accepts the command, reads the requested memory location and copies its contents onto the bus.

12. Linking the ComponentsMachine Cycles • Instruction Time (I-time) • The current instruction moves over the bus and into the instruction register.

13. Fig. 4.2a: A machine cycle(I-Time). The instruction control unit sends a fetch command over the bus to memory.

14. Fig. 4.2b: A machine cycle(I-Time). Memory responds by copying the contents of the requested memory location onto the bus.

15. Fig. 4.2c: A machine cycle(I-Time). The instruction moves into the instruction register.

16. Linking the CoponentsMachine Cycles • Execution Time (E-time) • The ICU activates the arithmetic and logic unit. • The ALU executes the instruction in the instruction register. • The ALU issues, over the bus, a command to fetch the contents of a specified memory location.

17. Linking The ComponentsMachine Cycles • Execution Time (E-time) • The memory controller reads the requested word and copies the contents onto the bus. • The data flow to a work register.

18. Fig. 4.2d: A machine cycle(E-Time). The arithmetic and logic unit executes the instruction in the instruction register.

19. Fig. 4.2e: A machine cycle(E-Time). The arithmetic and logic unit fetches the data.

20. Fig. 4.2f: A machine cycle(E-Time). The data value flows over the bus and into a work register.

21. Linking The ComponentsArchitecture • Architecture • The interconnections that link a computer’s components. • Single Bus Architecture • All components are linked to a common bus. • Multiple-Bus Architecture • Processor and Channel processing

22. Fig. 4.3: Microcomputers are constructed around a metal framework called a motherboard.

23. Fig. 4.4: The bus links the processor to a number of slots into which components can be plugged.

24. Fig. 4.5: Memory and peripheral devices are added by plugging a memory board or an interface board into one of the open slots.

25. Linking the ComponentsInterfaces • Each peripheral device has its own interface • The basic function of the interface is translation. • One side of the interface communicates with the computer • The other side is device dependent, communicating with the external device in its own terms.

26. Fig. 4.7: The function of an interface is to translate between internal and external form.

27. Fig. 4.5: With single-bus architecture all the components are linked to a common bus.

28. Linking the ComponentsChannels and Control Units • Microcomputers are designed for single users, so single-bus architecture is reasonable.

29. Channels and Control Units • Mainframes support multiple users concurrently. • Unlike the microcomputer, the mainframe processor is freed from controlling I/O. • Channel • A micro or minicomputer with its own processor • Can perform logical functions in parallel with the computer’s main processor.

30. Fig. 4.7: Device-independent functions are assigned to a channel and device-dependent functions are assigned to an I/O control unit.

31. Multiple- Bus Architecture • The processor manipulates data in memory. • A channel moves data between memory and a peripheral device. • Because a single-bus architecture provides only one physical data path, only one user can be supported at any one time. • Because a mainframe supports multiple users, a multiple-bus architecture is used.

32. Fig. 4.8a: Most mainframes use multiple-bus architecture. The processor starts an I/O operation by sending a signal to the channel.

33. Fig. 4.8b: Most mainframes use multiple-bus architecture. The channel handles the I/O operation and the processor turns to another program.

34. Fig. 4.8c: Most mainframes use multiple-bus architecture. The channel sends an interrupt to the processor to signal the end of the I/O operation.

35. Logical and Physical I/O • Primitive • A physical operation performed by an interface or a peripheral device. • Open • The process of initially establishing a link to a peripheral device.

36. Logical and Physical I/O • Logical I/O • The programmer’s view of I/O. • Physical I/O • The act of physically transferring a unit of data between memory and a peripheral device. • Access Method • A subroutine that performs application-dependent portions of an I/O operation.

37. Fig. 4.9: A programmer’s logical I/O request is converted to the appropriate physical I/O operation by the operating system.

38. Fig. 4.10: On some mainframes, application-dependent portions of the logical-to-physical translation are assigned to access methods.

39. Fig. 4.11: The linkage editor adds the access method to the load module at load time.

40. Fig. 4.12: Converting a logical I/O request to primitive physical commands.

41. Fig. 4.13: A message consists of a header, a body, and a trailer.

42. Networks • Network • two or more computers linked by communication lines • Network types • local area network (LAN) • wide area network (WAN)

43. Fig. 4.14: On a bus network server the, workstations, and various peripheral devices all share a common bus.

44. Fig. 4.15: In a hierarchical network the computers are linked to form a hierarchy.

45. Fig. 4.16: In a star network each host is linked to a central star machine.

46. Fig. 4.17: In a ring network the connections form a ring.

47. Fig. 4.18: A bridge links two or more similar networks. A gateway links dissimilar networks.

48. Network Management • A network operating system helps to manage the system. • each computer is a node • Each node has a unique address • messages routed from node to node • Polling • When 2 or more computers try to transmit data at the same time over the same line, their messages can interfere with each other. • With Polling the network server sends a polling signal to each workstation. • Messages are transmitted only in response to a polling signal.

49. Network Management • Collision detection • Allows the workstation to send messages whenever they want. • If 2 messages are transmitted at the same time, the signals interfere with each other. • The “collision” is detected electronically and the affected messages are retransmitted.

50. Network Management • Token Passing • The signal (the token) moves continuously around the network and a computer is allowed to transmit a message only when it holds the token.