Final Project Description

1. Final Project Description

2. Project Goal • To gain practice designing a large scale system on an FPGA that tackles a problem of significant scope. • To apply previously developed peripheral interfaces and components to a larger scale design. • To gain practice with compartmentalization of design pieces and clean interfaces – enabling multiple developers to be effectively utilized in a complex hardware / software system design. • The final project for this class will be a self-directed group project which will put to use the SOC design techniques that have been developed in the previous laboratories. Students should form into groups of 1, 2 or 3 , or 4 for the duration of the project.

3. Schedule

4. Grading Criteria • Project Proposal - Nov 16 5 • Critical Design Review (CDR) – Nov 30 15 • Initial Demonstration - Nov 30 20 • CDR Action item response - Dec 5 5 • Final Review & Demonstration – Dec 12 40 • Website 10 • Available by CDR • Updated with all documentation and project at final review

5. Requirements • The project should exercise at least 3 peripherals. • The project should utilize at least 1 new peripheral from the Spartan 3A DSP development board which has not been used yet. (Note: an external peripheral that the student is particularly interested in can be substituted if it can be obtained) • Camera • ADC • RF Wireless Link • VGA Interface • LCD Display • The project shall include • A microprocessor core • A "software" operation accelerated in hardware • Some custom hardware written in VHDL • Software, written in C for the microprocessor • A new IP Core (from COREGen, or external sources) that hasn't been used in class. • The project should be of significant scope, in accordance with this being a 1 month project in a 700 level Master's course. (Projects approved by instructors.)

6. Project Proposal • Attractive elements in a project: • Using hardware not available on the board • i.e., joystick, audio codec, accelerometer, receiver • Using a different FPGA board • i.e., Atlys, ML403, something available at work • Interesting signal processing algorithms: • “full” FM radio, camera algorithms • interesting concept or technique from an academic or industry paper

7. Tuners We have some of these available to use.. Students would wire from these to their FPGA board (slightly crude, but easily accomplished)

8. Tuners (2) • Interface defined by receiver chip on the schematic • Types of ideas: • Radio • Build a full, multi-band (AM, FM), radio • SIGINT: • Capture and demodulate FRS radio transmissions • Detect and display the presence of signals, create a waterfall display

9. ML403 Key Features • Xilinx Devices: • XC4VFX12-FF668-10C • PowerPC 405 integrated core (works with EDK very similar to MicroBlaze) • Memory: 64 MB DDR SDRAM, 8Mb ZBT SRAM, 64 Mb Flash, 4 kb IIC EEPROM • Connectors and Interfaces: • 2 Audio (In/Out, Microphone/Head Phone) • 3 USB Ports (2 Peripheral/1 Host) • DB 15 VGA Display • 10/100/1000 RJ-45 Ethernet Port • 64 Bit User Expansion Connector • Types of Ideas: • Linux-enabled FPGA system • Build a full MP3 player Two of these are available for students who would like to use them. They are large, (if slightly dated)

10. Atlys Key Features • Spartan 6 XC6SLX45 • 2 Channels of HDMI Video IN and Out • Ethernet PHY • AC-97 Audio Codec • DDR2 memory with integrated memory controller • Enables using Linux Two of these are available for students to use

11. Other Hardware • RF Interface, Camera, Display (on our board) • Memory on our board (next week) • Accelerometer, for example: • http://www.evbplus.com/accelerometer_3axis/tinybee_accelerometer_3axis.html • Digilent, various hardware interfaces: • http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 • Other ideas: www.google.com

12. What To Turn In : 11/16 : Proposal A brief (1-2 pages) description of the project. • Required Elements: • Introduction/Background: Summarize the project, and describe why an integrated SOC is an appropriate solution • System block diagram: Include both HW and SW blocks • Team Members (2-3 recommended, 1 or 4 allowed, but scope should be commensurate with team size) • Division of labor • Individuals receive grades, not the team, so please describe who you propose to be responsible for various portions of the project. If this changes during the project due to evolving requirements or difficulties, make sure to describe new responsibilities at CDR…etc.

13. CDR (11/30) • CDR • Prove that you have a fully designed implementation, ready for implementation • Prove that the difficult pieces will work • best proof: some basic implementation • Present design, risks, and schedule • Each team member should present

14. CDR Demonstrations (11/30) • Demonstrations are an opportunity to prove that progress has been made towards realizing the final project. Each student should demonstrate something at the CDR to show progress that has been made • Demonstration examples: • Does your project rely on an interface? Prove you have implemented its basic functionality. • Does your project utilize a new piece of hardware? Demonstrate a basic interface. • Are you implementing a signal processing algorithm? Prove it works in MATLAB • Maybe: demonstrate buggy, but nearly full capabilities • Maybe: demonstrate fully functional core capabilities, but without supporting user interfaces • In other words -- show us you’ve been working!

15. Final Project Presentation / Demo • Final Review • Briefly review design, highlight changes • Describe algorithms operation (teach us!) • Discuss interesting challenges or clever design approaches • Demonstrate a robust, finished project • Grading of this will generally be weighted 50/50 between good design decisions and functionality.  The project working as designed is important, but equally important are : • clean interfaces between components for easy debugging • appropriate compartmentalization which allows pieces to be designed / developed / tested independently • good synchronous design practices • Clear understanding of functionality for describing to the class and instructors